I'm new to the verilog. I receive following warning when I synthesize my code on the Xilinx 14.3
Synthesizing Unit
<Router_Debug>
.Related source file is "Router_Debug.v".
WARNING:Xst:646 - Signal
<P0_data_out<16:23>>
is assigned but never used. This unconnected signal will be trimmed during the optimization process.Unit
<Router_Debug>
synthesized.
File: Router_Debug.v
module Router_Debug(output wire signed [0:31]out_N,
output wire signed [0:7]out_E,
output wire signed [0:7]out_W,
output wire signed [0:7]out_S,
output wire signed [0:7]out_L,
input wire signed [0:7]in_N,
input wire signed [0:7]in_E,
input wire signed [0:7]in_W,
input wire signed [0:7]in_S,
input wire signed [0:7]in_L,
input clk);
wire signed [0:31]P0_data_out;
reg signed [0:31]P0_data_in;
wire signed [0:31]P1_data_out;
reg signed [0:31]P1_data_in;
wire signed[0:31]P2_data_out;
reg signed[0:31]P2_data_in;
wire signed[0:31]P3_data_out;
reg signed[0:31]P3_data_in;
wire signed[0:31]P4_data_out;
reg signed[0:31]P4_data_in;
always @ (*)
begin
P0_data_in[0:7]<=P1_data_out[0:7];
P0_data_in[8:15]<=P2_data_out[0:7];
P0_data_in[16:23]<=P3_data_out[0:7];
P0_data_in[24:31]<=P4_data_out[0:7];
P1_data_in[0:7]<=P0_data_out[0:7];
P1_data_in[8:15]<=P2_data_out[8:15];
P1_data_in[16:23]<=P3_data_out[8:15];
P1_data_in[24:31]<=P4_data_out[8:15];
P2_data_in[0:7]<=P0_data_out[8:15];
P2_data_in[8:15]<=P1_data_out[8:15];
P2_data_in[16:23]<=P3_data_out[16:23];
P2_data_in[24:31]<=P4_data_out[16:23];
P3_data_in[0:31]<=P0_data_out[16:23];
P3_data_in[8:15]<=P1_data_out[16:23];
P3_data_in[16:23]<=P2_data_out[16:23];
P3_data_in[24:31]<=P4_data_out[24:31];
P4_data_in[0:7]<=P0_data_out[24:31];
P4_data_in[8:15]<=P1_data_out[24:31];
P4_data_in[16:23]<=P2_data_out[24:31];
P4_data_in[24:31]<=P3_data_out[24:31];
end
Port_Debug P0(P0_data_out,P0_data_in,in_N,out_N,clk,3'd0);//mesh_size,3'd0);
Port_Debug P1(P1_data_out,P1_data_in,in_W,out_W,clk,3'd1);//mesh_size,3'd1);
Port_Debug P2(P2_data_out,P2_data_in,in_S,out_S,clk,3'd2);//mesh_size,3'd2);
Port_Debug P3(P3_data_out,P3_data_in,in_L,out_L,clk,3'd3);//mesh_size,3'd3);
Port_Debug P4(P4_data_out,P4_data_in,in_E,out_E,clk,3'd4);//mesh_size,3'd4)
endmodule
I've searched on the google and found relevant problem's solutions but that didn't help me. So any help will be much appreciated. Thanks!
I can't do much with your code because:
You have a code error in there:
You use non-blocking <=
assignments in a combinatorial block. That should be blocking =
.
You code style is unorthodox:
signed [0:7]
even works... output wire signed [0:31]out_N,
output wire signed [0:7]out_E,
output wire signed [0:7]out_W,
output wire signed [0:7]out_S,
...
Port_Debug(.portname0(P0_data_out),
.portname1(P0_data_in),
...
...............
There is an anomaly in your code:
P3_data_in[0:31]<=P0_data_out[16:23];
Does not match the pattern. You probably wanted: P3_data_in[0:7]<=P0_data_out[16:23];
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