RISC-V ADDI instruction

Question

I am currently working on implementing RV32I Base Instruction Set.

I had a question about ADDI instruction. In the manual, how to understand this clause "ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction."

Does it mean ADDI rd, rs1, 0 is equal to move content of rs1 to register specified by rd?

Answer 1

yes ADDI rd, rs1, 0 performs the operation :

rd <- rs1 + 0 , that is rd <- rs1

so ADDI rd, rs1, 0 performs MV rd, rs1

It does not performs a move (copy is a better word) of the content of rs1 to the register specified by rd as mentionned in the question. It performs a move (copy again) of the content of rs1 to the register rd.

With an example :

ADDI x3, x5, 0 will copy the content of x5 to x3 - and using the same name as above, in this example : rd is x3 and rs1 is x5 .

Answer 2

Yes, ADDI rd, rs1, 0 is the encoding of the MV rd, rs1 instruction.

Many encodings are possible, eg XORI rd, rs1, 0 would have the same effect.

The reason for specifying which is the chosen encoding is so a disassembler will output MV rd, rs1 when it sees ADDI rd, rs1, 0 , but XORI rd, rs1, 0 will still be disassembled as XORI rd, rs1, 0 .

Other instructions have specified encodings, such as NOP being ADDI x0, x0, 0 , rather than any of the other instructions which do nothing. Note: register 0 is magic . It always reads as zero, thus writes are lost.

MV instructions set one register's value equal to another register's value, so they would be better described as "copy", as @LiHenyuan wrote.

Answer 3

The mv x, y (move) pseudo-instruction is just an alias for addi x, y, 0 . That means it's syntactic sugar that is implemented inside the assembler.

Since the mv alias is resolved by the assembler mv doesn't have its own opcode and thus isn't a real instruction. Hence it's called a pseudo-instruction.

Using the mv pseudo-instruction arguably describes the purpose of your code more clearly. Certainly, it's slightly less to type and less to parse for a human.