LLVM Instruction Scheduling in RISC-V

Question

I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach.

Is MachineScheduler is better than ScheduleDAGRRList? If so, how can i enable MachineScheduler for RISC-V ?

I tried llc -enable-misched file.ll , but with no luck.

Answer 1

The RISC-V backend added support for the Machine Scheduler (MISched) in LLVM release 10.0.

https://releases.llvm.org/10.0.0/docs/ReleaseNotes.html

The TableGen SchedMachineModel descriptions in RISCVSchedRocket64.td describe it as an in-order processor.

// Rocket machine model for scheduling and other instruction cost heuristics.
def Rocket64Model : SchedMachineModel {
  let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
  let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
  let LoadLatency = 3;
  let MispredictPenalty = 3;
}

You can enable machine scheduling for rocket-rv64 with:

-O3 -mllvm -enable-misched -mllvm -enable-post-misched -mcpu=rocket-rv64