Check if genvar is odd in verilog

Question

I am new to verilog hdl, I would like to know how to write the following code right:

genvar cnt;
for( cnt = 0 ; cnt < 5 ; cnt = cnt + 1) begin
   if (cnt is odd) begin
     // do something
    end else begin
    // do something else
      end
end

Answer 1

I'm not sure why you'd need to do this in verilog. Verilog is an hardware description language not just another programming language.

To check if cnt is odd I suggest you just check the last bit of the variable.

If the last bit is 1 the number will be odd.

if (cnt[0]) begin
    //cnt is odd
    //do something
end else begin
    //cnt is even
    //do something else
end

Answer 2

一种方法是使用模运算符 ( % )：

if (cnt % 2)