verilog: a genvar 'i' following with width?

Question

module xxx
(
    input   wire    [`NUM+7:0]  dec_in,
    output  wire    [`NUM-1:0]  dec
);

generate
genvar i;
    for (i=0; i < `NUM; i=i+1) begin : 
        assign base = (dec_of_onehot >= i[`NUM-1:0]);
        assign bound = (dec_of_onehot <= i[`NUM-1:0]);
        assign onehot_of_dec[i]  = (base == 1'b1) && (bound == 1'b1);
    end
endgenerate

endmodule

What's the meaning of assign xxx? Does not contain variable definitions for base and bound but still works. and a genvar 'i' following with width?

Answer 1

base and bound are implicit 1-bit wire declarations for each iteration of the generate loop. Unless you name the begin/end generate block, they are local to each block.

I assume there must be variable declarations for the other variables that you did not show.

BTW, relying on implicit wire declarations is poor programming practice. It would be much clear to show the intent

genvar i;
    for (i=0; i < `NUM; i=i+1) begin
        wire base, bound;
        assign base = (dec_of_onehot >= i[`NUM-1:0]);
        assign bound = (dec_of_onehot <= i[`NUM-1:0]);
        assign onehot_of_dec[i]  = (base == 1'b1) && (bound == 1'b1);
    end