Dividing a verilog genvar

Question

So I'm building a tree in Verilog. The tree will assign element j of level i to the smaller of [j,j+1] of level i+1.

The issue here is I'm not sure how verilog treats the divide operator for genvar's:

genvar i,j;
generate
  for(i = LEVELS; i > 0; i--) begin
    for(j = 0; j < 2**i; j = j + 2) begin // 0..7 for level 3, 0..3 for level 2, 0..1 for level 1 and 0 for level 0
      assign tree[i-1][j/2] = tree[i][j] <operator> tree[i][j+1];
    end
  end
endgenerate

The issue here is I'm not sure that j/2 above will be floored so that 1/2 == 0. Anyone know if this is true?

Answer 1

This simulation demonstrates that, if j is odd, then j/2 will be floored:

module tb;

wire [7:0] tree [4];

genvar j;
generate
    for (j=1; j<8; j=j+2) begin
        assign tree[j/2] = j;
    end
endgenerate

initial begin
    #1;
    for (int k=0; k<4; k++) $display("tree[%0d] = %0d", k, tree[k]);
end

endmodule

Output:

tree[0] = 1
tree[1] = 3
tree[2] = 5
tree[3] = 7

In this code, j has only odd values: 1, 3, 5, 7.

So j/2 resolves to the even values: 0, 1, 2, 3.

---

As an aside: in your code, you can't have 1/2. j can only be 0,2,4,6... So, j/2 can only be 0,1,2,3...

Answer 2

integer division is always floored:

IEEE 1800-2017: 11.4.2: The integer division shall truncate any fractional part toward zero.

Answer 3

If all you need is j/2, why not just replace it with (j>>1)? There's less chance of tools misinterpreting it. LRM is not carved in stone, I've seen lots of CAD tools taking it to pretty irrational places.