output vhdl signal assignment

Question

I have this signal assignment for a case in the output. Can any one help me understand what it means?

comb_master_command:
    master_command_o <= '1' when  voltage_converted > V0VOLT and  voltage_converted <= V2VOLT else
                      '0';

So I understand '1' is assigned to master_command_o if voltage_converted > V0VOLT ...

but what does the and mean here?? and the next part voltage_converted <= V2VOLT is V2VOLT assigned to voltage_converted or is it a condition of voltage less then or equal to V2VOLT ?

Thanks in advance.

Answer 1

You have to read this line as:

master_command_o <= '1' when (voltage_converted > V0VOLT and voltage_converted <= V2VOLT)
                    else '0';

The and means that you need both conditions: voltage_converted > V0VOLT and voltage_converted <= V2VOLT to be valid. Meaning that voltage_converted is within the range: ] V0VOLT, V2VOLT ] will result master_command_o to be '1' else '0'