Structural Ring Oscillator VHDL

Question

I'm facing problems with the following ring oscillator code:

entity OSCILLATOR is
    port(   OUTPUT: out std_logic
    );
end entity OSCILLATOR;

architecture structural of OSCILLATOR is

component DEL_INV is
    generic(D: time);   
    port(   INPUT: in std_logic;
            OUTPUT: out std_logic   
        );
end component DEL_INV;

signal conn: std_logic := '0';
signal conn1: std_logic := '1';
signal conn2: std_logic := '0';
signal de: time := 2 ns;

begin
    INV1: DEL_INV generic map(de) port map (conn, conn1);
    INV2: DEL_INV generic map(de) port map (conn1, conn2);
    INV3: DEL_INV generic map(de) port map (conn2, conn);

    OUTPUT <= conn;

end architecture;

In particular, while simulating it, the output is always U. Can someone explain why?

Answer 1

The initial values assigned to the signals conn* , to ensure well-defined start condition in simulation, are overwritten at start by an 'U' driven by the OUTPUT on the DEL_INV module, and the simulation thus ends up stuck in all U .

One solution is to handle the initial value through the DEL_INV module with a generic that allows different initial OUTPUT values, and then use this initial value on the OUTPUT until the value is well defined as '0' or '1' , which can be detected through the is_x function.

Updated code for this is shown below. Note that I added the suggestions by Renaud Pacalet for for all: DEL_INV use entity work.DEL_INV(s); and inverter ( not ) in DEL_INV .

library ieee;
use ieee.std_logic_1164.all;

entity DEL_INV is
  generic(
    D: time;
    XOUT: std_logic);
  port(
    INPUT: in std_logic;
    OUTPUT: out std_logic);
end entity DEL_INV;

architecture s of DEL_INV is
  signal PRE : std_logic;
begin
  PRE <= (not INPUT) after D;
  OUTPUT <= XOUT when is_x(PRE) else PRE;  -- Drive XOUT if is_x to clean up
end architecture s;


library ieee;
use ieee.std_logic_1164.all;

entity OSCILLATOR is
  port(
    OUTPUT: out std_logic);
end entity OSCILLATOR;

architecture structural of OSCILLATOR is

component DEL_INV is
  generic(
    D: time;
    XOUT: std_logic);
  port(
    INPUT: in std_logic;
    OUTPUT: out std_logic);
end component DEL_INV;

for all: DEL_INV use entity work.DEL_INV(s);

signal conn  : std_logic;
signal conn1 : std_logic;
signal conn2 : std_logic;

constant DE : time := 2 ns;

begin

    INV1: DEL_INV generic map(de, '0') port map (conn, conn1);
    INV2: DEL_INV generic map(de, '1') port map (conn1, conn2);
    INV3: DEL_INV generic map(de, '0') port map (conn2, conn);

    OUTPUT <= conn;

end architecture;