Will OS request interrupt to device?

Question

Take UART as an example.

When UART received data, the UART device(chip) generates an interrupt, the SW interrupt handler will process this interrupt, ex: read data from HW buffer. This part is reasonable.

For TX case, will OS/driver generate an interrupt to the device (UART chip) to let UART chip know there are some data need to send out?

Answer 1

A typical way to handle UART input goes a bit further than you say:

When data has been received the UART generates a HW interrupt and the interrupt handler reads the data from UART and places it in a FIFO buffer, often a circular buffer.

At the higher level when the OS wants to receive data it looks at the input buffer to see if there is any data there.

This mechanism provides another layer of asynchronicity and it means that the input data flow control need only block the remote transmitter when the receiver's input buffer is (nearly) full.

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One typical way to handle output is this:

The UART generates a HW interrupt when it is ready to transmit data. The interrupt handler will then look at the FIFO output buffer and place the first item in the queue in the UART's transmit register. Otherwise if there is no data waiting to be transmitted the interrupt status is cleared.

At the higher level when the OS wants to transmit data it places the item in the output buffer and ensures that the UART will generate a HW interrupt when it is ready to transmit, which may be straight away.

This means that the output data flow is only blocked when the output buffer is full.

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Neither of these actually require a SW interrupt at the UART handling level. The SW interrupt is a convenient way for applications to communicate with the OS.

Answer 2

Device generate hardware interrupts not OS-es or drivers.

Generally communication hardware generate interrupts when:

1. It has got some data
2. It is ready to send data
3. It is in error condition.
4. It has ended the commucication (especially important for hardware with internal buffers like FIFOs)

If hardware uses DMA you may have another interrupts as well

5. End of DMA transaction
6. Half of the transaction
7. DMA error

Answer 3

To put things easier, here I check Linux 1.0 as the code base.

static void rs_stop(struct tty_struct *tty)
{
...
info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 
// you can see UART_IER_THRI is not here, the TX interrupt was disabled.
...
}

static void rs_start(struct tty_struct *tty)
{
    info->IER = (UART_IER_MSI | UART_IER_RLSI |
         UART_IER_THRI | UART_IER_RDI);
  // THRI is enabled here.
}