Makefile can't find my .cpp dependancy file

Question

Files makefile.vars I'm trying to compile 4 .cpp files and a header, while running through the compilation process so I can get the object files and the assembly file but the makefile is giving me an error that it can't find my original .cpp file. "No rule to make target Add.cpp needed by Add.s. Stop."

#include "makefile.vars"
$(Bin)Main: $(Objects)Add.o $(Objects)Subtract.o $(Objects)Multiply.o $(Objects)common.o $(Objects)Main.o
    $(GCC) $(Objects)Add.o
    $(Objects)Subtract.o
    $(Objects)Multiply.o
    $(Objects)common.o
    $(Objects)Main.o
    -o $(Bin)Main
clean:
    rm -rf $(Bin)/* $(Objects)/* $(Pre)/* $(Assembly)/*

$(Assembly)Add.s: $(Source)Add.cpp
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S  -o $(Source)Add.cpp  $(Assembly)Add.s
$(Assembly)Add.o: $(Source)Add.s
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $(Assembly)Add.s $(Objects)Add.o

$(Assembly)Subtract.s: $(Source)Subtract.cpp
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S -o $(Source)Subtract.cpp  $(Assembly)Subtract.s
$(Assembly)Subtract.o: $(Source)Subtract.s
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $(Assembly)Subtract.s $(Objects)Subtract.o

$(Assembly)Multiply.s: $(Source)Multiply.cpp
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S -o $(Source)Multiply.cpp  $(Assembly)Multiply.s
$(Assembly)/Multiply.o: $(Source)/Multiply.s
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $(Assembly)Multiply.s $(Objects)Multiply.o

$(Assembly)Main.s: $(Source)Main.cpp
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S -o $(Source)Main.cpp  $(Assembly)Main.s
$(Assembly)/Main.o: $(Source)/Main.s
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $(Assembly)Main.s  $(Objects)Main.o

$(Assembly)common.s: $(Header)common.h
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S -o $(Header)common.h  $(Assembly)common.s
$(Assembly)common.o: $(Source)common.s
    $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $(Assembly)common.s $(Objects)common.o

I want my files to be object files in the end that I can link.

Answer 1

Your problem is you're using the C/C++ preprocessor #include in a makefile. Makefiles are not C/C++ code.

In a makefile, a # introduces a comment line, so the rest of the line is ignored.

Also, make does not do anything special with quotes so you should not use them in non-recipe parts of makefiles (you should of course use them where needed in recipes, which are passed to the shell, because the shell does do special things with quotes).

Change:

#include "makefile.vars"

to:

include makefile.vars

ETA

Your next problem is because you have misused variables, so make can't create the dependency chain. Consider these rules:

$(Bin)Main: $(Objects)Add.o ...
        ...
$(Assembly)Add.s: $(Source)Add.cpp
        ...
$(Assembly)Add.o: $(Source)Add.s
        ...

The first rule tells make it can create $(Bin)Main from $(Objects)Add.o . The second says make can create $(Assembly)Add.s from $(Source)Add.cpp . The last rule tells make it can create $(Assembly)Add.o from $(Source)Add.s .

None of these rules tell make how to create $(Objects)Add.o (assuming that the variables Objects and Assembly do not have the same value).

And if you fix that, then you'll get a failure because none of your rules tell make how to build $(Source)Add.s which is the prerequisite of Add.o .

You need to use the same variables for the same target in all places; the final rule should be:

$(Objects)Add.o: $(Assembly)Add.s
        ...

ETA2

Also your rules are wrong: you are using -o $(Source)Add.cpp so you are asking the compiler to generate output that will overwrite your source file. I hope you see this edit before you fix your makefile enough to delete all your code.

ETA3

Your makefiles would be a lot simpler and a lot less prone to errors (and much easier to fix mistakes in) if you use pattern rules instead of duplicating all your text over and over; delete ALL your rules for building assembly and object files and add these two pattern rules:

(Assembly)%.s: $(Source)%.cpp
        $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -S -o $@ $<
$(Objects)%.o: $(Assembly)%.s
        $(GCC) $(DEBUG) $(GCC_FLAGS) $(INCLUDES) -c -o $@ $<