How to properly make my makefile to compile and run?

Question

The question is probably not the best one to describe my issue but I couldn't think of a better one. My makefile goes like this:

PROGRAM_NAME = prog

OBJECT_FILES = $(PROGRAM_NAME).o
CFLAGS = -O2 -Wall -g

$(PROGRAM_NAME) : $(OBJECT_FILES)
    gcc $(CFLAGS) -o $@ $(OBJECT_FILES)

$(PROGRAM_NAME).o : $(PROGRAM_NAME).c data.h
    gcc $(CFLAGS) -c $<

clean :
    $(RM) $(PROGRAM_NAME)
    $(RM) $(OBJECT_FILES)
    $(RM) *~ *.bak

run :
    @$(MAKE) && ./$(PROGRAM_NAME) $(ARGS)

When I want to compile and run I just do "make run". The issue with this is that my program handles the signal produced by Ctrl+Z and if I start my program with "make run", the signal will be sent to "make run" and not my program itself.

Basically, calling "make run" is not the same thing as calling directly "make && ./prog" because in the first case, "make run" will not terminate unless "prog" terminates first.

Is there a way around this?

Answer 1

You can simplify your 'run' target by having it depend on whether your program is up to date, and then simply run the program:

run:    ${PROGRAM_NAME}
        ./${PROGRAM} ${ARGS}

There's not much point in running make when you're already running make - at least, not in this context. Maybe for recursive operations (in different directories), but see ' Recursive Make Considered Harmful '.

Also, your makefile should normally provide a target ' all ' and it should normally the first and therefore default target.

Answer 2

Running from the makefile is a bit unusual. Are you, perhaps, trying to duplicate the "Compile and Run" Menu item that some IDE provide? Make is not well equipped to do that.

All the stuff that happens in the target commands happens in sub-processes that are not attached directly to the terminal, which is why make receives your key stroke.

Another thing to look at: usually the object-file to executable stage (linking) uses a different set of flags ( LDFLAGS and LIBS ) then the compile stage. In this simple example you can get away with it, but if you copy this makefile for use in a more complicated case you'll run into trouble.

Answer 3

If you're going to build and run over and over, You can use the history command to help with this:

# Run this once
make && ./foo

# Repeat last command
!!

Answer 4

As dmckee's answer said, make(1) is making something, not for compile-and-run.

Of course, nothing stops you for creating a shell alias make-run which does the intended ' make && ./prog args '.

Answer 5

You can try like this:

APP      = olupxtest

SRCS     = $(wildcard *.cpp)
OBJS     = $(SRCS:.cpp=.o)

CXXFLAGS = -g -fPIC -c
LDFLAGS  =
LIBS     =

.PHONY: all clean

all: clean $(APP) run

$(APP): $(OBJS)
        $(CXX) $(LDFLAGS) $^ $(LIBS) -o $@

clean:
        $(RM) $(OBJS) $(APP)

run:    ${APP}
        ./${APP} ${ARGS}

Here you have calling multiple rules for target: all: clean $(APP) run