OpenOCD doesn't open/listen on any ports, using an STM32 Nucleo board

Question

So I've been interested in learning embedded programming and just got my Nucleo F103RB(stm32) board. I want to avoid IDEs and work in terminal with open-source tools. I've been trying to follow this tutorial:

https://cycling-touring.net/2018/12/flashing-and-debugging-stm32-microcontrollers-under-linux

But when I'm typing

openocd -f board/st_nucleo_f103rb.cfg

I'm only getting this:

Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 1000 kHz
adapter_nsrst_delay: 100
none separate
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : clock speed 950 kHz
Info : STLINK v2 JTAG v29 API v2 SWIM v18 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.260766
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints

It is not telling me anything about listening on some ports, and in fact I cannot interface it when using telnet on port 3333 or 4444 which are the defaults one that OpenOCD is supposed to open. I've been trying this on OSX, and in a Linux (PopOs,) Virtual Machine. and I'm getting the same results. How can I get OpenOCD to "listen"?

I know it's a bit confused, but I'm completely noob in this and am a bit lost.

Answer 1

Openocd should listen right the way. In order to remove uncertainties regarding the version of openocd you built, I would suggest to try an already compiled one available from here :

I just tried in a Lubuntu x86_64 18.04 virtual machine hosted on Windows using the st_nucleo_f103rb.cfg configuration, and got:

sudo bin/openocd -f ./scripts/board/st_nucleo_f103rb.cfg 
xPack OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev (2019-07-17-11:25)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
srst_only separate srst_nogate srst_open_drain connect_deassert_srst

Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : STLINK V2J17S4 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.387457
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections

My stlink is at version 1, which does explain some differences in the messages being displayed.

If you can make it work, that means your house-built openocd may have an issue which will need to be investigated further - in the case your actual goal would be to compile openocd, and not becoming familiar with embedded systems. The exact git revision you compiled openocd from may be useful.

Answer 2

For now I will start with 0.9.0 that works great the same./bootstrap./configure make, you might have to add/enable some things in there./configure --help

ST-Link Programmer                      yes (auto)
CMSIS-DAP Compliant Debugger            yes (auto)
SEGGER J-Link Programmer                yes (auto)

at least the stlink in your case.

I will do stlink in a later edit

jlink.cfg

#
# SEGGER J-Link
#
# http://www.segger.com/jlink.html
#

interface jlink

transport select swd



# The serial number can be used to select a specific device in case more than
# one is connected to the host.
#
# Example: Select J-Link with serial number 123456789
#
# jlink serial 123456789

target.cfg

# script for stm32f1x family

#
# stm32 devices support both JTAG and SWD transports.
#
#source [find target/swj-dp.tcl]
# ARM Debug Interface V5 (ADI_V5) utility
# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
# SW-DP and JTAG-DP targets don't need to switch based
# on which transport is active.
#
# declare a JTAG or SWD Debug Access Point (DAP)
# based on the transport in use with this session.
# You can't access JTAG ops when SWD is active, etc.

# params are currently what "jtag newtap" uses
# because OpenOCD internals are still strongly biased
# to JTAG ....  but for SWD, "irlen" etc are ignored,
# and the internals work differently

# for now, ignore non-JTAG and non-SWD transports
# (e.g. initial flash programming via SPI or UART)

# split out "chip" and "tag" so we can someday handle
# them more uniformly irlen too...)

if [catch {transport select}] {
  echo "Error: unable to select a session transport. Can't continue."
  shutdown
}

proc swj_newdap {chip tag args} {
 if [using_hla] {
     eval hla newtap $chip $tag $args
 } elseif [using_jtag] {
     eval jtag newtap $chip $tag $args
 } elseif [using_swd] {
     eval swd newdap $chip $tag $args
 }
}


#source [find mem_helper.tcl]
# Helper for common memory read/modify/write procedures

# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
    set value ""
    mem2array value 32 $reg 1
    return $value(0)
}

add_usage_text mrw "address"
add_help_text mrw "Returns value of word in memory."

proc mrb {reg} {
    set value ""
    mem2array value 8 $reg 1
    return $value(0)
}

add_usage_text mrb "address"
add_help_text mrb "Returns value of byte in memory."

# mmw: "memory modify word", updates value of $reg
#       $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
    set old [mrw $reg]
    set new [expr ($old & ~$clearbits) | $setbits]
    mww $reg $new
}

add_usage_text mmw "address setbits clearbits"
add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"



if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f1x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some STM32F100s)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0008 Section 26.6.3
      set _CPUTAPID 0x3ba00477
   } {
      # this is the SW-DP tap id not the jtag tap id
      set _CPUTAPID 0x1ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

if { [info exists BSTAPID] } {
   # FIXME this never gets used to override defaults...
   set _BSTAPID $BSTAPID
} else {
  # See STM Document RM0008
  # Section 29.6.2
  # Low density devices, Rev A
  set _BSTAPID1 0x06412041
  # Medium density devices, Rev A
  set _BSTAPID2 0x06410041
  # Medium density devices, Rev B and Rev Z
  set _BSTAPID3 0x16410041
  set _BSTAPID4 0x06420041
  # High density devices, Rev A
  set _BSTAPID5 0x06414041
  # Connectivity line devices, Rev A and Rev Z
  set _BSTAPID6 0x06418041
  # XL line devices, Rev A
  set _BSTAPID7 0x06430041
  # VL line devices, Rev A and Z In medium-density and high-density value line devices
  set _BSTAPID8 0x06420041
  # VL line devices, Rev A
  set _BSTAPID9 0x06428041
}

if {[using_jtag]} {
 swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
    -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
    -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
    -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
    -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter_khz 1000

adapter_nsrst_delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
    # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
    #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
    mmw 0xE0042004 0x00000307 0
}

$_TARGETNAME configure -event trace-config {
    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
    # change this value accordingly to configure trace pins
    # assignment
    mmw 0xE0042004 0x00000020 0
}

Note that there is no mention of telnet nor 4444, but it defaults to being there.

window 1

sudo openocd -f jlink.cfg -f target.cfg 
Open On-Chip Debugger 0.9.0 (2020-01-14-14:35)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : JLink SWD mode enabled
swd
adapter speed: 1000 kHz
adapter_nsrst_delay: 100
none separate
cortex_m reset_config sysresetreq
Info : J-Link ARM-OB STM32 compiled Jun 30 2009 11:14:15
Info : J-Link caps 0x88ea5833
Info : J-Link hw version 70000
Info : J-Link hw type J-Link
Info : J-Link max mem block 15344
Info : J-Link configuration
Info : USB-Address: 0x0
Info : Kickstart power on JTAG-pin 19: 0x0
Info : Vref = 3.300 TCK = 1 TDI = 1 TDO = 1 TMS = 0 SRST = 1 TRST = 1
Info : J-Link JTAG Interface ready
Info : clock speed 1000 kHz
Info : SWD IDCODE 0x1ba01477
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints

window 2

sudo telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> 

Then window 1 says

Info : accepting 'telnet' connection on tcp/4444

window 2

> halt
target state: halted
target halted due to debug-request, current mode: Thread 
xPSR: 0x41000000 pc: 0x080000d4 msp: 0x20003fe8
> mdw 0 20
0x00000000: 20004000 080000c1 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 
0x00000020: 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 
0x00000040: 080000c7 080000c7 080000c7 080000c7 
> 
> halt
target state: halted
target halted due to debug-request, current mode: Thread 
xPSR: 0x41000000 pc: 0x080000d4 msp: 0x20003fe8
> mdw 0 20
0x00000000: 20004000 080000c1 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 
0x00000020: 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 080000c7 
0x00000040: 080000c7 080000c7 080000c7 080000c7 
> flash write_image erase blinker.elf  
auto erase enabled
device id = 0x20036410
flash size = 64kbytes
wrote 1024 bytes from file blinker.elf in 0.111541s (8.965 KiB/s)
> reset
> 

And the led is blinking

Get into trouble use reset halt.

And from here replace the jlink.cfg with one of the stlinks that matches your board you can use lsusb to perhaps tell

Bus 003 Device 023: ID 1366:0101 SEGGER J-Link PLUS
Bus 003 Device 024: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB)

grep 374b *
stlink-v2-1.cfg:hla_vid_pid 0x0483 0x374b

Sorted out the 0.10.0 issue.

So pretty much built per that pages directions...

sudo apt remove openocd
sudo apt build-dep openocd
git clone https://git.code.sf.net/p/openocd/code openocd-code
cd openocd-code
./bootstrap
./configure
make
sudo make install

(I didn't install, I don't want to trash my custom build)

jlink.cfg (for 0.10.0)

#
# SEGGER J-Link
#
# http://www.segger.com/jlink.html
#

interface jlink

transport select swd


# The serial number can be used to select a specific device in case more than
# one is connected to the host.
#
# Example: Select J-Link with serial number 123456789
#
# jlink serial 123456789

target.cfg

# script for stm32f1x family

#
# stm32 devices support both JTAG and SWD transports.
#
#source [find target/swj-dp.tcl]

# ARM Debug Interface V5 (ADI_V5) utility
# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
# SW-DP and JTAG-DP targets don't need to switch based
# on which transport is active.
#
# declare a JTAG or SWD Debug Access Point (DAP)
# based on the transport in use with this session.
# You can't access JTAG ops when SWD is active, etc.

# params are currently what "jtag newtap" uses
# because OpenOCD internals are still strongly biased
# to JTAG ....  but for SWD, "irlen" etc are ignored,
# and the internals work differently

# for now, ignore non-JTAG and non-SWD transports
# (e.g. initial flash programming via SPI or UART)

# split out "chip" and "tag" so we can someday handle
# them more uniformly irlen too...)

if [catch {transport select}] {
  echo "Error: unable to select a session transport. Can't continue."
  shutdown
}

proc swj_newdap {chip tag args} {
 if [using_hla] {
     eval hla newtap $chip $tag $args
 } elseif [using_jtag] {
     eval jtag newtap $chip $tag $args
 } elseif [using_swd] {
     eval swd newdap $chip $tag $args
 }
}


#source [find mem_helper.tcl]

# Helper for common memory read/modify/write procedures

# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
    set value ""
    mem2array value 32 $reg 1
    return $value(0)
}

add_usage_text mrw "address"
add_help_text mrw "Returns value of word in memory."

# mrh: "memory read halfword", returns value of $reg
proc mrh {reg} {
    set value ""
    mem2array value 16 $reg 1
    return $value(0)
}

add_usage_text mrh "address"
add_help_text mrh "Returns value of halfword in memory."

# mrb: "memory read byte", returns value of $reg
proc mrb {reg} {
    set value ""
    mem2array value 8 $reg 1
    return $value(0)
}

add_usage_text mrb "address"
add_help_text mrb "Returns value of byte in memory."

# mmw: "memory modify word", updates value of $reg
#       $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
    set old [mrw $reg]
    set new [expr ($old & ~$clearbits) | $setbits]
    mww $reg $new
}

add_usage_text mmw "address setbits clearbits"
add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f1x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some STM32F100s)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
    set _FLASH_SIZE $FLASH_SIZE
} else {
    # autodetect size
    set _FLASH_SIZE 0
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0008 Section 26.6.3
      set _CPUTAPID 0x3ba00477
   } {
      # this is the SW-DP tap id not the jtag tap id
      set _CPUTAPID 0x1ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

if {[using_jtag]} {
   jtag newtap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter speed 1000

adapter srst delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
    # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
    #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
    mmw 0xE0042004 0x00000307 0
}

$_TARGETNAME configure -event trace-config {
    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
    # change this value accordingly to configure trace pins
    # assignment
    mmw 0xE0042004 0x00000020 0
}

Same commands as before

sudo ../openocd-code/src/openocd -f jlink.cfg  -f stm32f1x.cfg 
Open On-Chip Debugger 0.10.0+dev-01180-g10b39c3-dirty (2020-04-13-21:29)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
swd
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link ARM-OB STM32 compiled Jun 30 2009 11:14:15
Info : Hardware version: 7.00
Info : VTarget = 3.300 V
Info : clock speed 1000 kHz
Info : SWD DPIDR 0x1ba01477
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : starting gdb server for stm32f1x.cpu on 3333
Info : Listening on port 3333 for gdb connections

It does mention listening on the port, and same for the other window, and the led blinks.

So now with the debug header on a big nucleo card. lsusb shows

Bus 001 Device 016: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB)

so

cat stlink-v2-1.cfg 
echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
source [find interface/stlink.cfg]

so

window 1

sudo ../openocd-code/src/openocd -f stlink.cfg  -f stm32f1x.cfg 
Open On-Chip Debugger 0.10.0+dev-01180-g10b39c3-dirty (2020-04-13-21:29)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : STLINK V2J28M18 (API v2) VID:PID 0483:374B
Info : Target voltage: 3.247989
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : starting gdb server for stm32f1x.cpu on 3333
Info : Listening on port 3333 for gdb connections

window 2

sudo telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> halt
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x080000ac msp: 0x20000ff0
> flash write_image erase blinker.elf
device id = 0x20036410
flash size = 64kbytes
auto erase enabled
wrote 1024 bytes from file blinker.elf in 0.100447s (9.955 KiB/s)

> reset
> halt
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08000054 msp: 0x20000ff0
> 

led blinks then with the halt led stops blinking

usually the interface is the easy part and you can swap out that config with another once you get one working. the issue I had with 0.10.0 here is that it needed

transport select swd

because it made a comment about jtag and to use transport select if you wanted a different interface, and that was the trick.

and that is what I had in my 0.9.0 jlink.cfg file.

On your mac, depending on the age you should be able to use a live thumb drive (or cdrom) of mint or ubuntu or whatever and do these things to see if it is a macos thing or something else.

apt-get install openocd (or build from sources) then create/copy the files over, seems like you have telnet issues so even if you can telnet localhost 4444 and get in that is a win, halt, mdw 0 20, things like that, win win win.

I mentioned in a comment but the first thing I do when I get a nucleo or discovery board is get the firmware updater from ST, it is Java based so works on Windows, Linux, Mac and even though the one you find may be old it checks online for the firmware I don't think it carries with it a version that stops at some point. I then update the firmware on the nucleo card. I had issues in the early days of the nucleo cards with Linux that the thumb drive would only allow one write to happen then you had to unplug and replug the card, and other similar issues that firmware fixed, these days they ship with a working version, but as a habit I do this.

Despite what the st board docs say I have used the nucleo headers on non-st chips. But I have a number of the five dollar purple jlink swd stm32 cards (type those three words in your search and increase your odds, have gotten some through Amazon even (not from Asia) as well as some on eBay from Asia), I don't have to look up the pinout when I use those and they just work. The nucleo I have to look up the pinout every time.

So if either 0.9.0 or 0.10.0 works on Linux on your laptop with a live usb (not via virtual machine,) then it is not your hardware. it is something to do with software. If it doesn't work on Linux on your computer then maybe you have a hardawre issue with your stlink or other.

What chip is on your nucleo board? That can make a difference I was mislead by yor F103RB thing that is related to the MCU that is on the debugger end, what is the complete name of your board NUCLEO-FXXXXXXX?Is it really an F103xxxx target mcu? Which is what I demonstrated here, hang on...

sudo ../openocd-code/src/openocd -f stlink.cfg  -f stm32f1x.cfg 
Open On-Chip Debugger 0.10.0+dev-01180-g10b39c3-dirty (2020-04-13-21:29)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : STLINK V2J28M18 (API v2) VID:PID 0483:374B
Info : Target voltage: 3.248358
Warn : UNEXPECTED idcode: 0x5ba02477
Error: expected 1 of 1: 0x1ba01477

these files used against an STM32F7xxx which is whose debugger end I was using...

grep -ri 5ba02477 *
target/renesas_s7g2.cfg:    set _CPU_SWD_TAPID 0x5ba02477
target/stm32f7x.cfg:      set _CPUTAPID 0x5ba02477

Anyway, it is possible, using the files essentially unmodified from the repo provides telnet access on 4444 with or without it printing that fact out during the connection. you need to do something like

gdb_port 0
tcl_port 0

to disable access to those ports.