How to verify constraints of LR/SC sequence (RISC-V ISA)

Question

I have read RISC-V spec about RV32A extension, i got a question that: how the CPU can verify constraints of LR/SC sequence if the program is executed these instructions:

lr.w x6,x0,(x0)
jal x0,dest
.......
beq x0,x0,-1
.......
dest:
sc.w x1,x6,(x0)

The spec said that "For the sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and SC instructions can only contain other instructions from the base “I” instruction set, excluding loads,stores, backward jumps or taken backward branches, JALR, FENCE, FENCE.I, and SYSTEM instructions.".

So if the program jumps over beq(taken backward branch which violated the constraint above),how the CPU can detect 'beq' appear in LR/SC sequences. In my design, the hardware can not detect 'beq' if the program executes above instructions, then SC can store data into the data memory successfully, but it actually should cause a store fail.

Answer 1

The beq isn't part of the dynamic code executed between LR and SC. This is not a violation of the constraint you quoted because the beq doesn't execute . It's just sitting in memory doing nothing, like all the other potentially megabytes of memory you jump over with a jal .

Dynamic means in order of execution, static means in memory-address order.

Also, the CPU isn't required to make such sequences always fail, it's merely allowed to. So a programmer should avoid them if they want to make sure that every RISC-V CPUs can get through the LR/SC sequence without aborting because of some specific illegal condition like executing a backwards beq .