Is There Any Limit to How Wide 2 VHDL Numbers Can Be To Add Them In 1 Clock Cycle?

Question

I am considering adding two 1024-bit numbers in VHDL.

Ideally, I would like to hit a 100 MHz clock frequency.

Target is a Xilinx 7-series.

When you add 2 numbers together, there are inevitably carry bits. Since carry bits on the left cannot be computed until bits on the right have been calculated, to me it seems there should be a limit on how wide a register can be and still be added in 1 clock cycle.

Here are my questions:

1.) Do FPGAs add numbers in this way? Or do they have some way of performing addition that does not suffer from the carry problem?

2.) Is there a limit to the width? If so, is 1024 within the realm of reason for a 100 MHz clock, or is that asking for trouble?

Answer 1

Maybe this works, have not tried it:

library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Calculator is
  generic(
            num_length : integer := 1024
         ); 
    port(
            EN: in std_logic;
            clk: in std_logic;
            number1 : in std_logic_vector((num_length) - 1 downto 0);
            number2 : in std_logic_vector((num_length) - 1 downto 0);
            CTRL    : in std_logic_vector(2 downto 0);
            result  : out std_logic_vector(((num_length * 2) - 1) downto 0));
end Calculator;
    
architecture Beh of Calculator is
    signal temp : unsigned(((num_length * 2) - 1) downto 0) := (others => '0');
 begin
 
    result <= std_logic_vector(temp);
 
    process(EN, clk)
        begin
            if EN ='0' then
                temp <= (others => '0');
            elsif (rising_edge(clk))then
            
                case ctrl is
                    when "00" => temp <= unsigned(number1) + unsigned(number2);
                    when "01" => temp <= unsigned(number1) - unsigned(number2);
                    when "10" => temp <= unsigned(number1) * unsigned(number2);
                    when "11" => temp <= unsigned(number1) / unsigned(number2);
                end case;
            end if;                 
    end process;
end Beh;

Answer 2

No. You just need to choose a suitably long clock cycle.

Practically, though there is no fundamental limit, for any given cycle time, there will be some limit which depends on the FPGA technology.

At 1024 bits, I'd look at breaking the addition and pipelining it.

Implemented as a single cycle, I would expect a 1024 bit addition to have a speed somewhere around 5, maybe 10 MHz. (This would be easy to check: synthesise one and look at the timing reports!)

Pipelining is not the only approach to overcoming that limit.

There are also "fast adder" architectures like carry look-ahead, carry-save (details via the usual sources)... these pretty much fell out of fashion when FPGAs built fast carry chains into the LUT fabric, but they may have niche uses such as yours. However they may not be optimally supported by synthesis since (for most purposes) the fast carry chain is adequate.