How do I configure a permanent shell in GNU Make running on Windows?

Question

I am maintaining a cross-platform project (Linux/Windows/32/64) with hundreds of C and C ++ files. For this I am using a single makefile using GNU Make. My problem happens when I compile in Windows because the Visual Studio (cl) compiler forces me to set an enviroment by calling vcvarsall.bat [platform_type] and this process is executed every time I compile a file with which the total process is extremely expensive in time.

Partial makefile

# C object file generation rule
../int/$(PROJECT)/%.o: ../%.c 
ifeq ($(OS),Windows_NT)
    @vcvarsall.bat x86 & cl $(CFLAGS) -c $(subst /,\,$<)
else
    @gcc $(CFLAGS) -c $<
endif
    

The sentence @vcvarsall.bat x86 is executed whenever each file is compiled. Is there a way where this statement is only executed once and that all successive shells inherit this ?

Thanks !

Answer 1

This is one of the truly annoying things about development on Windows, for sure.

It's not possible for a shell to "pass on" its values after it exits, to the next shell. It's also not possible for make to start a single shell then run all the rules' recipes in that one shell.

All you can do is set the values once in the parent shell, then invoke make from there. The simplest way to do this is have a .bat file that does the proper thing, then invokes make. You can have a similarly-named shell script on POSIX systems that doesn't do anything except invoke make.

If you really don't want to do that, then the only option is to use recursive make invocations where the top-level make will run the vcvarsall script then invoke a sub-make which will compile all the things.