I am working with a 64 bit RISC processor, and I have question can we access the lower 32 part of the 64 bit register separately? As in case of AArch64 where x0 is for entire 64-bit register and w0 corresponds to the 32 bit part of the same register.
Do we have this kind of feature in RISC-V?
64-bit RISC-V has 64-bit registers. Instead of using a different register name to indicate 32-bit operations, they use a different mnemonic (eg addw
for a single 32-bit word width vs. add
for the full register). Most(?) instructions are available in a 32-bit form as well as the full-width form.
int add(int a,int b){
return a+b;
}
long long add64(long long a,long long b){
return a+b;
}
Compiled by GCC10.2 for rv64gc on Godbolt
add:
addw a0,a0,a1
ret
add64:
add a0,a0,a1
ret
See also Does it makes sense for a clean-slate 64-bit instruction set only have 64-bit registers, if we don't care about backwards compat? re: how it's just a matter of asm syntax for MIPS/RISC-V with different mnemonics vs. AArch64 with reg names.
(Although having special mnemonics makes it clearer that not every 64-bit instruction necessarily has a 32-bit operand-size version. eg auipc
doesn't need a form that truncates an address to 32-bit.)
See also Why did RV64 introduce new opcodes for 32-bit operations instead of the 64-bit ones re: the design decision. Further related:
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