make: hierarchical make file

Question

(disclaimer: I am used to scons ... I am somewhat unexperienced with make)

Context: I am using Eclipse CDT which generates makefiles.

Let's say I have a project directory 'lib' and 2 build configurations 'Debug' and 'Release'. Eclipse CDT gracefully generates a makefile for each build configuration. The said makefiles end-up residing in 'Debug' and 'Release' folders.

Now, what I want to do is have a makefile in the folder 'lib' which calls the makefiles 'Debug/makefile' and 'Release/makefile'.

How do I do that?

I want to be able to launch 'make' in the folder 'lib' and both configurations would be called with the specified target(s).

Solution Based on all the great input gathered here, I devised the following:

MAKE=make
BUILDS=Release Debug
TARGETS=all clean

$(TARGETS):
    @for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done

$(BUILDS):
    @for t in $(TARGETS) ; do $(MAKE) -C $@ $$t ; done

%:
    @for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done

Answer 1

depends on what is "calls". You want to either

include $(BUILD)/Makefile

or

$(MAKE) -C $(BUILD) $@

or some such. I'd guess you want the latter. Maybe something like

release debug:
    $(MAKE) -C $@

You get the idea.

More examples:

BUILDS=release debug
TARGETS=all clean

$(TARGETS):
    for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done

$(BUILDS):
    for t in $(TARGETS) ; do $(MAKE) -C $@ $$t ; done

Answer 2

Since you mention "the specified target(s)", I suggest:

%:
    $(MAKE) -C Debug $@
    $(MAKE) -C Release $@

If that's too general, you can replace the % with $(TARGETS), where TARGETS is something you define, a list of all the things you'd ever want to do this with.

Answer 3

all: release debug

release:
   $(MAKE) -C ../Release

debug:
   $(MAKE) -C ../Debug

I'm assuming they're all on the same level. The path must be from where you call Make.

Answer 4

Have different targets that invoke the makefile in the two directories.

all: debug product

debug:
        $(MAKE) -f debug/Makefile

product:
        $(MAKE) -f product/Makefile