Compiling C File with Assembler file dependencies

Question

I have a file app.c that makes calls to two external functions, ie. func_asm1 and func_asm2. Both functions are in a seperate Assembler file, ie. func_asm1.S and func_asm2.S. Furthermore, I have two header files, ie. func_asm1.h and func_asm2.h where the interface of the two assembler functions are defined:

extern void func_asm1(unsigned int *r, const unsigned int *a);

The main file app.c includes the two header func_asm1.h and func_asm2.h, my make file looks at the moment as follows but I does not work... Anyone an idea what could be wrong?

CC  = bin/arm-elf-gcc
AS  = bin/arm-elf-as
SFLAGS=-S -O2

func_asm1.o: func_asm1.S
    $(AS) -o $@ $< 

func_asm2.o: func_asm2.S
    $(AS) -o $@ $<

app.o: app.c app.h func_asm1.h func_asm2.h
    $(CC) $(SFLAGS) app.c -o app.o func_asm1.o func_asm2.o

Many thanks for your help!

Answer 1

I think your makefile has wrong dependencies:

The last part should be something like:

func_asm1.o: func_asm1.S
$(AS) -o $@ $< 

func_asm2.o: func_asm2.S
$(AS) -o $@ $<

app: app.c app.h func_asm1.h func_asm2.h func_asm1.o func_asm2.o
$(CC) $(SFLAGS) app.c -o app.o func_asm1.o func_asm2.o

Why ? Because func_asm1.o and func2.o depends their source code (I am assuming that you don't use func_asm.h in the assembler source code) On the other hand, app.o depends on its source code (app.c), its header files (app.h, func_asm1.h and func_asm2.h) and the object code for the assembly files. Note that you are compiling AND linking in that part of the makefile so if the object code for the assembly files change, you have to relink the application and therefore execute those lines.

As I've been pointed out in the comments, you should check the parameters passed to gcc (the -S flag passed in SFLAGS )

Answer 2

The -S option tells gcc to generate assembler output rather than an object, which is not what you want.

When you use gcc, just pass the assembler files to gcc:

.S.o:
    $(CC) $(ASFLAGS) -o $@ -c $<

.c.o:
    $(CC) $(CFLAGS) -o $@ -c $<

app: app.o func_asm1.o func_asm2.o
    $(CC) $(LDFLAGS) -o $@ $^

For dependency tracking, I'd extend the two compile rules with -MD -MP and include the generated * .d files in my Makefile, rather than listing headers explicitly.