I'm playing around some tutorial code from this OpenCV 2 Cookbook . The code doesn't come with any Makefiles, and I'd like to create a Makefile that can Make all of the files in the codebase . My plan is to compile all the files with profiling, and then make a script that runs all the executables and collects the gprof results. Then, I can get some intuition for the computation time of various OpenCV functions.
The codebase is arranged like this: tutorial_code/Chapter[1-10]/*.cpp
Each .cpp
file is self-sufficient and can be compiled without linking against other modules in this codebase. (There are a few small header-only libraries, though.)
Here are a couple things that I'm stuck up on:
$(EXEC)
in a Makefile represents a file that is the culmination of much of the building effort. However, in my case, I want to create a separate $(EXEC)
for each .cpp
file. I think I'm close to getting this right, but so far my Makefile just generates *.o
but not *.out
SOURCES = $(wildcard *.cpp)
is a way to "collect" the set of cpp files in the current directory. It would make sense that SOURCES = $(wildcard */*.cpp)
would drill down and grab all .cpp
files in the subdirectories. It doesn't seem to work, though. Starting from this tutorial , I set up a Makefile that implements the proposed functionality. It doesn't quite work... $(wildcard */*.cpp)
doesn't seem to drill down into directories, and I'm not sure how to do something like $<
and $@
to refer to basefilename.o
and to create basefilename.out
.
CC = g++
CC_FLAGS = -w `pkg-config opencv --cflags`
LINK = g++
LINKOPTS = -pg `pkg-config opencv --libs`
SOURCES = $(wildcard */*.cpp)
OBJECTS = $(SOURCES:.cpp=.o)
EXEC = $(SOURCES:.cpp=.out)
%.out: %.o
$(LINK) $< $(LINKOPTS) -o $@
%.o: %.cpp
$(CC) -c $(CC_FLAGS) $< -o $@
clean:
rm -f $(EXEC) $(OBJECTS)
tutorial_code/Chapter[1-10]
directories and creates one Makefile for each directory. Then, I'd make an other function in the script to call Make once in each directory. The idea of doing one grand Makefile sounds like more fun, though. EDIT: This does work if I use SOURCES = $(wildcard *.cpp)
and place the Makefile in the same directory where cpp
files are located. However, I'm still trying to figure out how to have $(wildcard */*.cpp)
drill down into subdirectories.
EDIT 2: The Makefile shown above now works properly. To see the earlier version, feel free to scroll through the edit history.
You can write a version of wildcard
that works recursively to any depth using only make
functions:
find-recursive = \
$(wildcard $1/$2) \
$(foreach f,$(wildcard $1/*/.),\
$(call find-recursive,$(patsubst %/.,%,$f),$2))
SOURCES = $(call find-recursive,.,*.cpp)
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