[英]AlwaysError when running a testbench on a synchronizer
我在運行測試台以及在兩個現有D-FF上構建的同步器時遇到此錯誤。
File "/home/runner/design.py", line 28, in Sync
@always_seq(clk.posedge, reset=reset)
File "/usr/share/myhdl-0.8/lib/python/myhdl/_always_seq.py", line 76, in _always_seq_decorator
raise AlwaysSeqError(_error.ArgType)
myhdl.AlwaysError: decorated object should be a classic (non-generator) function
我的測試台概述如下
from myhdl import *
from random import randrange
HALF_PERIOD = delay(10) ### This makes a 20-ns clock signal
ACTIVE_HIGH = 1
G_DELAY = delay(15)
def Main():
### Signal declaration
clk, d, dout = [Signal(intbv(0)) for i in range(3)]
reset = ResetSignal(1,active=ACTIVE_HIGH,async=True)
### Module Instantiation
S1 = Sync(dout, d, clk,reset)
### Clk generator
@always(HALF_PERIOD)
def ClkGen():
clk.next = not clk
### TB def
@instance
def Driver():
yield(HALF_PERIOD)
reset.next = 0
for i in range(4):
yield(G_DELAY)
d.next = not d
raise StopSimulation
return ClkGen, Driver, S1
m1 = traceSignals(Main)
sim = Simulation(m1)
sim.run()
我的同步器編碼如下。
from myhdl import *
from DFF import *
def Sync(dout,din,clk,reset):
""" The module consists of two FFs with one internal signal
External signals
dout : output
din : input
clk : input
Internal signal:
F2F : output-to-input signal that connects two FFs together
"""
### Connectivity
F2F = Signal(intbv(0))
F1 = DFF(F2F,din,clk,reset)
F2 = DFF(dout,F2F,clk,reset)
### Function
@always_seq(clk.posedge,reset=reset)
def SyncLogic():
if reset:
F2F.next = 0
dout.next = 0
else:
F2F.next = din
yield(WIRE_DELAY)
dout.next = F2F
return SyncLogic
FF原型編碼如下。
from myhdl import *
def DFF(dout,din,clk,reset):
@always_seq(clk.posedge, reset=reset)
def Flogic():
if reset:
dout.next = 0
else:
dout.next = din
return Flogic
該測試平台確實可以與我之前編寫的類似測試平台(略有修改)一起使用,但是在將兩個模塊組合在一起時卻無法正常工作。 請澄清。 謝謝。
要模擬線路延遲,請在信號中使用“延遲”參數。
更改
@always_seq(clk.posedge,reset=reset)
def SyncLogic():
if reset:
F2F.next = 0
dout.next = 0
else:
F2F.next = din
yield(WIRE_DELAY)
dout.next = F2F
return SyncLogic
至:
dout = Signal(<type>, delay=WIRE_DELAY)
# ...
@always_seq(clk.posedge, reset=reset)
def synclogic():
dout.next = din
使用“ always_seq”時,無需定義重置(它將自動添加)。 如果要顯式定義重置,請使用“ @always(clock.posedge,reset.negedge)”。
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