[英]AlwaysError when running a testbench on a synchronizer
I encountered this error when running a testbench, together with a synchronizer built on two existing D-FFs. 我在运行测试台以及在两个现有D-FF上构建的同步器时遇到此错误。
File "/home/runner/design.py", line 28, in Sync
@always_seq(clk.posedge, reset=reset)
File "/usr/share/myhdl-0.8/lib/python/myhdl/_always_seq.py", line 76, in _always_seq_decorator
raise AlwaysSeqError(_error.ArgType)
myhdl.AlwaysError: decorated object should be a classic (non-generator) function
My testbench is outlined as follows 我的测试台概述如下
from myhdl import *
from random import randrange
HALF_PERIOD = delay(10) ### This makes a 20-ns clock signal
ACTIVE_HIGH = 1
G_DELAY = delay(15)
def Main():
### Signal declaration
clk, d, dout = [Signal(intbv(0)) for i in range(3)]
reset = ResetSignal(1,active=ACTIVE_HIGH,async=True)
### Module Instantiation
S1 = Sync(dout, d, clk,reset)
### Clk generator
@always(HALF_PERIOD)
def ClkGen():
clk.next = not clk
### TB def
@instance
def Driver():
yield(HALF_PERIOD)
reset.next = 0
for i in range(4):
yield(G_DELAY)
d.next = not d
raise StopSimulation
return ClkGen, Driver, S1
m1 = traceSignals(Main)
sim = Simulation(m1)
sim.run()
And my synchronizer is coded as follows. 我的同步器编码如下。
from myhdl import *
from DFF import *
def Sync(dout,din,clk,reset):
""" The module consists of two FFs with one internal signal
External signals
dout : output
din : input
clk : input
Internal signal:
F2F : output-to-input signal that connects two FFs together
"""
### Connectivity
F2F = Signal(intbv(0))
F1 = DFF(F2F,din,clk,reset)
F2 = DFF(dout,F2F,clk,reset)
### Function
@always_seq(clk.posedge,reset=reset)
def SyncLogic():
if reset:
F2F.next = 0
dout.next = 0
else:
F2F.next = din
yield(WIRE_DELAY)
dout.next = F2F
return SyncLogic
and the FF prototype is coded as follows. FF原型编码如下。
from myhdl import *
def DFF(dout,din,clk,reset):
@always_seq(clk.posedge, reset=reset)
def Flogic():
if reset:
dout.next = 0
else:
dout.next = din
return Flogic
The testbench did work with the similar testbench I coded earlier(with slight modification), but it didn't work when combining two modules together. 该测试平台确实可以与我之前编写的类似测试平台(略有修改)一起使用,但是在将两个模块组合在一起时却无法正常工作。 Please clarify.
请澄清。 Thank you.
谢谢。
To model a wire delay, use the "delay" argument in the Signal. 要模拟线路延迟,请在信号中使用“延迟”参数。
change 更改
@always_seq(clk.posedge,reset=reset)
def SyncLogic():
if reset:
F2F.next = 0
dout.next = 0
else:
F2F.next = din
yield(WIRE_DELAY)
dout.next = F2F
return SyncLogic
to: 至:
dout = Signal(<type>, delay=WIRE_DELAY)
# ...
@always_seq(clk.posedge, reset=reset)
def synclogic():
dout.next = din
With the "always_seq" don't define the reset (it is automatically added). 使用“ always_seq”时,无需定义重置(它将自动添加)。 If you want to explicitly define the reset use "@always(clock.posedge, reset.negedge)".
如果要显式定义重置,请使用“ @always(clock.posedge,reset.negedge)”。
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