MyHDL：無法將Signal.intbv.max轉換為VHDL

Question

我是python和MyHDL的新手，所以我首先將舊的VHDL項目轉換為MyHDL。 這個項目是一個vga計時器，可以接受任何寬度，高度和頻率（前提是它們實際上可以與顯示器配合使用）。 由於以下原因，它無法成功轉換為VHDL或Verilog：

h_count.val.max  # line 30
v_count.val.max  # line 33

我可以很好地打印它們的值，這樣它們就可以確定為整數，但是如果用它們的文字值替換它們，那么它將正確轉換。 我在myhdl問題跟蹤器中找不到關於此的任何信息，但是由於新手的錯誤，我不想添加錯誤的問題。 有使用Signal.val.max的正確方法還是我只是避免使用它？ 這是完整的代碼：

from myhdl import Signal, intbv, always_comb, always, toVHDL


def vga_timer(clk, x, y, h_sync, v_sync, vidon, width=800, height=600, frequency=72,
          left_buffer=0, right_buffer=0, top_buffer=0, bottom_buffer=0):
    # load vga constants by resolution
    resolution = (width, height, frequency)
    supported_resolutions = {(640, 480, 60): (16, 96, 48, 10, 2, 33, 0),
                         (800, 600, 60): (40, 128, 88, 1, 4, 23, 1),
                         (800, 600, 72): (56, 120, 64, 37, 6, 23, 1),
                         (1024, 768, 60): (24, 136, 160, 3, 6, 29, 0),
                         (1280, 720, 60): (72, 80, 216, 3, 5, 22, 1),
                         (1920, 1080, 60): (88, 44, 148, 4, 5, 36, 1)}
    assert resolution in supported_resolutions, "%ix%i @ %ifps not a supported resolution" % (width, height, frequency)
    screen_constants = supported_resolutions.get(resolution)

    # h for horizontal variables and signals, v for vertical constants and signals
    h_front_porch, h_sync_width, h_back_porch, v_front_porch, v_sync_width, v_back_porch, polarity = screen_constants

    h_count = Signal(intbv(0, 0, width + h_front_porch + h_sync_width + h_back_porch))
    v_count = Signal(intbv(0, 0, height + v_front_porch + v_sync_width + v_back_porch))

    print(h_count.val.max)
    print(v_count.val.max)

    @always(clk.posedge)
    def counters():
        h_count.next = h_count + 1
        v_count.next = v_count
        if h_count == 1040 - 1:  # h_count.val.max - 1:
            h_count.next = 0
            v_count.next = v_count + 1
            if v_count == 666 - 1:  # v_count.val.max - 1:
                v_count.next = 0

    # determines h_sync and v_sync
    @always_comb
    def sync_pulses():
        h_sync_left = width - left_buffer + h_front_porch
        h_sync_right = h_sync_left + h_sync_width
        h_sync.next = polarity
        if h_sync_left <= h_count and h_count < h_sync_right:
             h_sync.next = not polarity

        v_sync_left = height - top_buffer + v_front_porch
        v_sync_right = v_sync_left + v_sync_width
        v_sync.next = polarity
        if v_sync_left <= v_count and v_count < v_sync_right:
            v_sync.next = not polarity

    @always_comb
    def blanking():
        vidon.next = 0
        if h_count < width - left_buffer - right_buffer and v_count < height - top_buffer - bottom_buffer:
            vidon.next = 1

    @always_comb
    def x_y_adjust():
        # x and y are only used when vidon = 1. during this time x = h_count and y = v_count
        x.next = h_count[len(x.val):]
        y.next = v_count[len(y.val):]

    return counters, sync_pulses, blanking, x_y_adjust

width = 800
height = 600
frequency = 72

clk = Signal(bool(0))
x = Signal(intbv(0)[(width-1).bit_length():])
y = Signal(intbv(0)[(height-1).bit_length():])
h_sync = Signal(bool(0))
v_sync = Signal(bool(0))
vidon = Signal(bool(0))

vga_timer_inst = toVHDL(vga_timer, clk, x, y, h_sync, v_sync, vidon, width, height, frequency)

也歡迎對我的代碼提出任何其他建議。

Answer 1

您可能現在已經發現了這一點，但是如果您想要可轉換的代碼，則不能在組合或順序塊中使用信號質量（最小，最大，位數等）。 但是，您可以在這些塊之外的常量分配中使用它們。 因此，如果您用這些代替print語句： h_counter_max = h_count.val.max - 1 v_counter_max = v_count.val.max - 1您可以在第30和33行的測試中使用h_counter_max和v_counter_max 。

Answer 2

可以在最新版本中使用min ， max屬性。