RisingEdge示例不適用於Chisel3中的模塊輸入信號

Question

在Chisel文檔中，我們有一個上升沿檢測方法的例子，定義如下：

      def risingedge(x: Bool) = x && !RegNext(x)

所有示例代碼都可以在我的github 項目blp上找到 。

如果我在聲明如下的輸入信號上使用它：

class RisingEdge extends Module {
  val io = IO(new Bundle{
    val sclk = Input(Bool())
    val redge = Output(Bool())
    val fedge = Output(Bool())
  })

  // seems to not work with icarus + cocotb
  def risingedge(x: Bool) = x && !RegNext(x)
  def fallingedge(x: Bool) = !x && RegNext(x)
  // works with icarus + cocotb
  //def risingedge(x: Bool) = x && !RegNext(RegNext(x))
  //def fallingedge(x: Bool) = !x && RegNext(RegNext(x))

  io.redge :=  risingedge(io.sclk)
  io.fedge := fallingedge(io.sclk)
}

有了這個icarus / cocotb測試台：

class RisingEdge(object):
    def __init__(self, dut, clock):
        self._dut = dut
        self._clock_thread = cocotb.fork(clock.start())

    @cocotb.coroutine
    def reset(self):
        short_per = Timer(100, units="ns")
        self._dut.reset <= 1
        self._dut.io_sclk <= 0
        yield short_per
        self._dut.reset <= 0
        yield short_per

@cocotb.test()
def test_rising_edge(dut):
    dut._log.info("Launching RisingEdge test")
    redge = RisingEdge(dut, Clock(dut.clock, 1, "ns")) 
    yield redge.reset()
    cwait = Timer(10, "ns")
    for i in range(100):
        dut.io_sclk <= 1
        yield cwait
        dut.io_sclk <= 0
        yield cwait

我永遠不會在io.redge和io.fedge上獲得上升的脈沖。 要獲得脈沖，我必須更改risingedge的定義如下：

  def risingedge(x: Bool) = x && !RegNext(RegNext(x))

使用雙RegNext（）：

使用簡單的RegNext（）：

這是正常的行為嗎？

[編輯：我用上面給出的github示例修改了源代碼示例]

Answer 1

我不確定伊卡洛斯，但使用默認的Treadle模擬器進行這樣的測試。

class RisingEdgeTest extends FreeSpec {
  "debug should toggle" in {
    iotesters.Driver.execute(Array("-tiwv"), () => new SlaveSpi) { c =>
      new PeekPokeTester(c) {
        for (i <- 0 until 10) {
          poke(c.io.csn, i % 2)
          println(s"debug is ${peek(c.io.debug)}")
          step(1)
        }
      }
    }
  }
}

我看到了輸出

[info] [0.002] debug is 0
[info] [0.002] debug is 1
[info] [0.002] debug is 0
[info] [0.003] debug is 1
[info] [0.003] debug is 0
[info] [0.003] debug is 1
[info] [0.004] debug is 0
[info] [0.004] debug is 1
[info] [0.005] debug is 0
[info] [0.005] debug is 1

波形看起來像

你能解釋一下你認為這應該是什么樣子嗎？