[英]RisingEdge example doesn't work for module input signal in Chisel3
In Chisel documentation we have an example of rising edge detection method defined as following : 在Chisel文档中,我们有一个上升沿检测方法的例子,定义如下:
def risingedge(x: Bool) = x && !RegNext(x)
All example code is available on my github project blp . 所有示例代码都可以在我的github 项目blp上找到 。
If I use it on an Input signal declared as following : 如果我在声明如下的输入信号上使用它:
class RisingEdge extends Module {
val io = IO(new Bundle{
val sclk = Input(Bool())
val redge = Output(Bool())
val fedge = Output(Bool())
})
// seems to not work with icarus + cocotb
def risingedge(x: Bool) = x && !RegNext(x)
def fallingedge(x: Bool) = !x && RegNext(x)
// works with icarus + cocotb
//def risingedge(x: Bool) = x && !RegNext(RegNext(x))
//def fallingedge(x: Bool) = !x && RegNext(RegNext(x))
io.redge := risingedge(io.sclk)
io.fedge := fallingedge(io.sclk)
}
With this icarus/cocotb testbench : 有了这个icarus / cocotb测试台:
class RisingEdge(object):
def __init__(self, dut, clock):
self._dut = dut
self._clock_thread = cocotb.fork(clock.start())
@cocotb.coroutine
def reset(self):
short_per = Timer(100, units="ns")
self._dut.reset <= 1
self._dut.io_sclk <= 0
yield short_per
self._dut.reset <= 0
yield short_per
@cocotb.test()
def test_rising_edge(dut):
dut._log.info("Launching RisingEdge test")
redge = RisingEdge(dut, Clock(dut.clock, 1, "ns"))
yield redge.reset()
cwait = Timer(10, "ns")
for i in range(100):
dut.io_sclk <= 1
yield cwait
dut.io_sclk <= 0
yield cwait
I will never get rising pulses on io.redge and io.fedge. 我永远不会在io.redge和io.fedge上获得上升的脉冲。 To get the pulse I have to change the definition of risingedge as following :
要获得脉冲,我必须更改risingedge的定义如下:
def risingedge(x: Bool) = x && !RegNext(RegNext(x))
With dual RegNext() : 使用双RegNext():
With simple RegNext() : 使用简单的RegNext():
Is it a normal behavior ? 这是正常的行为吗?
[Edit: I modified source example with the github example given above] [编辑:我用上面给出的github示例修改了源代码示例]
I'm not sure about Icarus, but using the default Treadle simulator for a test like this. 我不确定伊卡洛斯,但使用默认的Treadle模拟器进行这样的测试。
class RisingEdgeTest extends FreeSpec {
"debug should toggle" in {
iotesters.Driver.execute(Array("-tiwv"), () => new SlaveSpi) { c =>
new PeekPokeTester(c) {
for (i <- 0 until 10) {
poke(c.io.csn, i % 2)
println(s"debug is ${peek(c.io.debug)}")
step(1)
}
}
}
}
}
I see the output 我看到了输出
[info] [0.002] debug is 0
[info] [0.002] debug is 1
[info] [0.002] debug is 0
[info] [0.003] debug is 1
[info] [0.003] debug is 0
[info] [0.003] debug is 1
[info] [0.004] debug is 0
[info] [0.004] debug is 1
[info] [0.005] debug is 0
[info] [0.005] debug is 1
And the wave form looks like 波形看起来像
Can you explain what you think this should look like. 你能解释一下你认为这应该是什么样子吗?
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