VHDL简单代码不起作用

Question

I am trying to make a simple register. The input bus brings 256 bits and the register simply has to record 32 bits on all of its 8 outputs. I don't understand why it doesn't work. It should have a synchronous load and clear and an asynchronous load and clear.

I tested it in a testbench. It doesn't change any of the values on the outputs. I performed the test with all of the control signals aload,sload,aclr and sclr separately. Nothing..

VHDL Module Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity VecReg is
    port (
                clk, sload, aload, sclr, aclr : in STD_LOGIC;
                D : in std_logic_vector(255 downto 0);
                Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 : out std_logic_vector(31 downto 0)
            );
end entity VecReg;

architecture VecRegArch of VecReg is
begin
    a1 : process(aload,aclr)
        begin
            if(aload = '1') then
                Q0 <= D(31 downto 0);
                Q1 <= D(63 downto 32);
                Q2 <= D(95 downto 64);
                Q3 <= D(127 downto 96);
                Q4 <= D(159 downto 128);
                Q5 <= D(191 downto 160);
                Q6 <= D(223 downto 192);
                Q7 <= D(255 downto 224);
            elsif(aclr = '1') then
                Q0 <= x"00000000";
                Q1 <= x"00000000";
                Q2 <= x"00000000";
                Q3 <= x"00000000";
                Q4 <= x"00000000";
                Q5 <= x"00000000";
                Q6 <= x"00000000";
                Q7 <= x"00000000";
            end if;
    end process a1;

    main : process(clk)
        begin
            if (rising_edge(clk)) and (sload = '1') then
                Q7 <= D(255 downto 224);
                Q6 <= D(223 downto 192);
                Q5 <= D(191 downto 160);
                Q4 <= D(159 downto 128);
                Q3 <= D(127 downto 96);
                Q2 <= D(95 downto 64);
                Q1 <= D(63 downto 32);
                Q0 <= D(31 downto 0);
            end if;
            if (rising_edge(clk)) and (sclr = '1') then
                Q0 <= x"00000000";
                Q1 <= x"00000000";
                Q2 <= x"00000000";
                Q3 <= x"00000000";
                Q4 <= x"00000000";
                Q5 <= x"00000000";
                Q6 <= x"00000000";
                Q7 <= x"00000000";
            end if;
    end process main;
end architecture VecRegArch;

VHDL testbench code:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY imame IS
END imame;

ARCHITECTURE behavior OF imame IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT VecReg
PORT(
     clk : IN  std_logic;
     sload : IN  std_logic;
     aload : IN  std_logic;
     sclr : IN  std_logic;
     aclr : IN  std_logic;
     D : IN  std_logic_vector(255 downto 0);
     Q0 : OUT  std_logic_vector(31 downto 0);
     Q1 : OUT  std_logic_vector(31 downto 0);
     Q2 : OUT  std_logic_vector(31 downto 0);
     Q3 : OUT  std_logic_vector(31 downto 0);
     Q4 : OUT  std_logic_vector(31 downto 0);
     Q5 : OUT  std_logic_vector(31 downto 0);
     Q6 : OUT  std_logic_vector(31 downto 0);
     Q7 : OUT  std_logic_vector(31 downto 0)
    );
END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal sload : std_logic := '0';
   signal aload : std_logic := '0';
   signal sclr : std_logic := '0';
   signal aclr : std_logic := '0';
   signal D : std_logic_vector(255 downto 0) := (others => '0');

    --Outputs
   signal Q0 : std_logic_vector(31 downto 0);
   signal Q1 : std_logic_vector(31 downto 0);
   signal Q2 : std_logic_vector(31 downto 0);
   signal Q3 : std_logic_vector(31 downto 0);
   signal Q4 : std_logic_vector(31 downto 0);
   signal Q5 : std_logic_vector(31 downto 0);
   signal Q6 : std_logic_vector(31 downto 0);
   signal Q7 : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_period : time := 100 us;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: VecReg PORT MAP (
          clk => clk,
          sload => sload,
          aload => aload,
          sclr => sclr,
          aclr => aclr,
          D => D,
          Q0 => Q0,
          Q1 => Q1,
          Q2 => Q2,
          Q3 => Q3,
          Q4 => Q4,
          Q5 => Q5,
          Q6 => Q6,
          Q7 => Q7
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
        aload <= '0';
        sload <= '0';
        aclr <= '0';
        sclr <= '0';
  wait for 500 us;
    D <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
        wait for 40 us;
        aload <= '1';
        wait for 1000 us;
        aload <= '0';
       --wait for 60 ns;

        --sload <= '0';
        --aload <= '0';
        --aclr <= '1';
        --wait for 200 ns;
        --sclr <= '1';
        --wait for 300 ns;
        --D <= x"1010111010101110101011101010111010101110101011101010111010101110";
        --aload <= '1';
        --wait for 400 ns;
        --aclr <= '1';
   end process;

END;

Answer 1

In the entity VecReg you have two processes both of which have drivers for Q0 through Q7. The resolution of the two drivers is 'U's.

Consolidate the a1 and main processes or give them their own set of signals to assign.

Making one process:

COMBINED:
    process (aload, aclr, clk)
    begin
        if(aload = '1') then
            Q0 <= D(31 downto 0);
            Q1 <= D(63 downto 32);
            Q2 <= D(95 downto 64);
            Q3 <= D(127 downto 96);
            Q4 <= D(159 downto 128);
            Q5 <= D(191 downto 160);
            Q6 <= D(223 downto 192);
            Q7 <= D(255 downto 224);
        elsif(aclr = '1') then
            Q0 <= x"00000000";
            Q1 <= x"00000000";
            Q2 <= x"00000000";
            Q3 <= x"00000000";
            Q4 <= x"00000000";
            Q5 <= x"00000000";
            Q6 <= x"00000000";
            Q7 <= x"00000000";
        elsif (rising_edge(clk)) then
            if sclr = '1' then
                Q0 <= x"00000000";
                Q1 <= x"00000000";
                Q2 <= x"00000000";
                Q3 <= x"00000000";
                Q4 <= x"00000000";
                Q5 <= x"00000000";
                Q6 <= x"00000000";
                Q7 <= x"00000000";
            elsif sload = '1' then
                Q7 <= D(255 downto 224);
                Q6 <= D(223 downto 192);
                Q5 <= D(191 downto 160);
                Q4 <= D(159 downto 128);
                Q3 <= D(127 downto 96);
                Q2 <= D(95 downto 64);
                Q1 <= D(63 downto 32);
                Q0 <= D(31 downto 0);
            end if;
        end if;      
    end process;

And commenting out processes a1 and main gives:

(clickable)