电线声明后的localparam

Question

For a very strange reason (scripts we use) I need to be able to declare a localparam AFTER I declare wires and regs in a module:

module blah (clk, rst, in, out);

  input        clk;
  input        rst;
  input  [2:0] in;
  output [3:0] out;

  wire         res;

  localparam NUMBER=5;


...

is this legal verilog code? I would also appreciate a link to the relevant seciton in the documentation. Thanks!

Answer 1

This is valid Verilog (2001). Verilog 2001 saw the introduction of localparam , for all versions it is still syntactically valid to use parameter in this context. localparam indicates that it can not be overridden.

Usage can be seen in section 23.10 Overriding module parameters of SystemVerilog IEEE Std 1800-2012 .

From IEEE 1800-2012:

For example:

module generic_fifo
    #(MSB=3, LSB=0)        // parameter port list parameters
    (input  wire  [MSB:LSB] in,
     input  wire            clk, read, write, reset,
     output logic [MSB:LSB] out,
     output logic           full, empty );

  parameter   DEPTH=4; // module item parameter

  localparam FIFO_MSB = DEPTH*MSB;
  localparam FIFO_LSB = LSB;
    // These constants are local, and cannot be overridden.
    // They can be affected by altering the value parameters above

  logic [FIFO_MSB:FIFO_LSB] fifo;
  logic [LOG2(DEPTH):0] depth;

  always @(posedge clk or posedge reset) begin
    casez ({read,write,reset})
      // implementation of fifo
    endcase
  end
endmodule

Answer 2

Exactly. As per the Verilog IEEE Std 1364-2001 , you can use localparam in your Verilog code. It can be declared after wire declaration, no problem for that.