[英]Difference between "parameter" and "localparam"
I'm writing a project with Verilog and want to use parameter<\/code> to define some parameter in my module.
我正在用 Verilog 编写一个项目,并希望使用
parameter<\/code>在我的模块中定义一些参数。
But when I read in some source code,
localparam<\/code> sometimes is used instead of
parameter<\/code> .
但是当我阅读一些源代码时,有时会使用
localparam<\/code>而不是
parameter<\/code> 。
What's difference between them?他们之间有什么区别?
"
Generally, the idea behind the localparam<\/code> (added to the Verilog-2001 standard) is to protect value of
localparam<\/code> from accidental or incorrect redefinition by an end-user (unlike a
parameter<\/code> value, this value can't be modified by parameter redefinition or by a
defparam<\/code> statement).
通常,
localparam<\/code>背后的想法(添加到 Verilog-2001 标准)是为了保护
localparam<\/code>的值免受最终用户意外或不正确的重新定义(与
parameter<\/code>值不同,此值不能通过参数重新定义或通过
defparam<\/code>声明)。
Based on IEEE 1364-2005 (ch. 4.10.2):基于 IEEE 1364-2005(第 4.10.2 章):
Verilog HDL local parameters are identical to parameters except that they cannot directly be modified by defparam statements or module instance parameter value assignments<\/strong> . Verilog HDL 本地参数与参数相同,只是它们不能通过 defparam 语句或模块实例参数值分配直接修改<\/strong>。 Local parameters can be assigned constant expressions containing parameters, which can be modified with defparam statements or module instance parameter value assignments.
可以为局部参数分配包含参数的常量表达式,可以使用 defparam 语句或模块实例参数值分配来修改。
<\/blockquote>
Additionally, in SystemVerilog ( IEEE 1800-2012<\/a> (ch. 6.20.4)):此外,在 SystemVerilog (
IEEE 1800-2012<\/a> (ch. 6.20.4)) 中:
<\/blockquote>
If you want to learn more about this topic, I'd recommend you Clifford E. Cummings paper "
New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)<\/a> ".如果您想了解有关此主题的更多信息,我建议您阅读 Clifford E. Cummings 的论文“
用于创建参数化模型的新 Verilog-2001 技术(或 Down With `define and Death of a defparam!)<\/a> ”。
"
Minimal example<\/strong>最小的例子<\/strong>
Here is an example of what Qiu mentioned.这是邱提到的一个例子。
In a RAM, the memory size is a function of the word and address sizes.在 RAM 中,内存大小是字和地址大小的函数。
So if the parent module specifies word and address size, it should not be able to specify the memory size as well.因此,如果父模块指定字和地址大小,它应该也不能指定内存大小。
module myram #(
parameter WORD_SIZE = 1,
parameter ADDR_SIZE = 1
) (
input wire [ADDR_SIZE-1:0] addr,
inout wire [WORD_SIZE-1:0] data,
// ...
);
localparam MEM_SIZE = WORD_SIZE * (1 << ADDR_SIZE);
// Use MEM_SIZE several times in block.
...
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