[英]How can generate the 32-bit RISCV form chisel soure. What are the required modifications?
According to the RISCV toolchain, we are generating the verilog files for Rocketchip as 64-bit. 根据RISCV工具链,我们正在为Rocketchip生成64位的Verilog文件。 but we need 32-bit RISCV rocket chip.
但是我们需要32位RISCV火箭芯片。 For that what are requirements and modifications in scala and chisel files.
为此,在scala和凿子文件中有什么要求和修改。
Is it possible to generate the 32-bit Rocket core to do so. 是否可以生成32位Rocket核心。
Rocket is a RV64 implementation. 火箭是RV64实现。 Unfortunately it does not have a simple switch to make it RV32.
不幸的是,它没有一个简单的开关即可制成RV32。 Making it RV32 will require some modification, hopefully small.
使其成为RV32将需要进行一些修改,希望很小。
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