使用Sigasi编辑器的VHDL中的灵敏度列表不完整

Question

Currently, I try to develop my VHDL skills and therefore I use the Sigasi plugin for Eclipse to write some VHDL code. Sigasi is a great tool, but there is one thing, which is bothering me, though. Constantly, Sigasi tosses warnings about incomplete sensitivity lists in process definitions, which are not justified from my point of view. One example is the following entity with the corresponding architecture. It's the description of a ring shift register

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RingShiftReg is
    generic(
        WIDTH : integer := 8
    );
    port(
        clock     : in  std_ulogic;
        reset     : in  std_ulogic;
        set       : in  std_ulogic;
        initValue : in  std_ulogic_vector(WIDTH - 1 downto 0);
        value     : out std_ulogic_vector(WIDTH - 1 downto 0)
    );
end;

architecture ringShiftRegArch of RingShiftReg is
    signal innerValue : std_ulogic_vector(WIDTH - 1 downto 0);
begin
    P1: process(clock, reset)
    begin
        if reset = '1' then
            innerValue <= (others => '0');
        elsif rising_edge(clock) then
            if set = '1' then
                innerValue <= initValue;
            end if;
        else
            innerValue <= innerValue(WIDTH - 2 downto 0) & innerValue(WIDTH - 1);
        end if;
    end process;
    value <= innerValue;
end ringShiftRegArch;

The Sigasi Linter claims that the sensitivity list of process P1 is incomplete, because the signal innerValue is missing. But in my opinion, it's not necessary to put innerValue in the sensitivity list, because it's totally dependent from clock and reset .

What is correct, now?

Answer 1

To make it short, your

else
  innerValue <= ... 
end if;

does not make sense in classical digital hardware because in this context your else means:

• clock or reset (or both) changed, and
• reset is not equal to '1' , and
• this is not a rising edge of clock .

So, it can be:

• a falling edge of reset , or
• a falling edge of clock while reset equals '0' .

Probably not what you intended. If it is what you intended, you should try to find another target technology. Classical digital hardware cannot achieve this because there are no multi-clocks, multi-edges, registers in ASIC standard cells libraries or in FPGAs.

Answer 2

Did you perhaps mean this?

elsif rising_edge(clock) then
  if set = '1' then
    innerValue <= initValue;
  else
    innerValue <= innerValue(WIDTH - 2 downto 0) & innerValue(WIDTH - 1);
  end if;
end if;