如何在 Chisel3 中初始化 Mem 的数据

Question

有没有什么简单的方法可以从文件中初始化 Mem 的数据（类似于 Verilog 中的“readmemh”）？

Answer 1

There is now a mechanism in the chisel stack to annotate memories to use readmemh or readmemb in simulation. Check out the documentation in the Chisel Wiki

Also, see here in Chisel Testers for concrete usage examples

Answer 2

There is no way built in to Chisel to do this. One of the guiding philosophies of Chisel is that what you simulate is what you build into an ASIC. Since there is no way in an ASIC to initialize an SRAM, there's no way to initialize memories in Chisel.

You can work around this by using a Reg of Vec (which can be initialized). If the target design is an ASIC, you could create a library that uses a state machine to initialize a given Mem after reset. If the target design is an FPGA, you could use BlackBox and just write Verilog for the Mem.

Answer 3

Attending the ASPIRE retreat this week, I heard that there is a way to code parameterized black boxes in Chisel that can have both:
1) Verilog code attached to it (so you could use $readmemh to initialize the ROM), and
2) Scala code attached to it (so that the firrtl-interpreter can simulate the ROM).
I don't know how to do either of these yet. Perhaps Jack or others can elaborate.

Answer 4

The following function is an approximation to Verilog's readmemh:

object Tools {

  def readmemh(path: String): Array[BigInt] = {
    val buffer = new ArrayBuffer[BigInt]
    for (line <- Source.fromFile(path).getLines) {
      val tokens: Array[String] = line.split("(//)").map(_.trim)
      if (tokens.length > 0 && tokens(0) != "") {
        val i = Integer.parseInt(tokens(0), 16)
        buffer.append(i)
      }
    }
    buffer.toArray
  }
}

And then in SpinalHDL

  rom.initialContent = Tools.readmemh(romfile)

or Chisel3:

  VecInit(Tools.readmemh(romfile))