如何在Chisel3中生成线束

Question

In Chisel2 there's seems to be a way to generate harness judging by this question .

It seems that the simulation mechanism is a bit different between Chisel2 and Chisel3. Quoted from the Chisel3 wiki :

Chisel2 was capable of directly generating a C++ simulation from the Chisel code, or a harness for use with a vcs simulation. Chisel3 relies on verilator to generate the C++ simulation from the Verilog output of firrtl. See the Chisel3 README for directions on installing verilator.

My question is: Is there a way in Chisel3 to generate verilog harness, similar to Chisel2?

Answer 1

I think you might take a look at src/main/scala/dsptools/tester/VerilogTbDump.scala in the dsptools project . The tb stands for test-bench. You may be able to find some clues on getting started. Or hopefully someone else will come along with a better answer.