[英]Synchronous Counter using JK flip-flop not behaves as expected
I'm trying to do an exercise in the book "Verilog HDL" by Sanir Panikkar: design a synchronous counter using JK flip-flop.我正在尝试在 Sanir Panikkar 的“Verilog HDL”一书中做一个练习:使用 JK 触发器设计同步计数器。
JK flip-flop circuit provided in the book:书中提供的JK触发器电路:
I believe there's a mistake in the above circuit: Input to the 3 AND gate should be Q0, Q1, Q2 from left to right, respectively;我认为上面的电路有一个错误:3与门的输入从左到右分别是Q0、Q1、Q2; not Q1, Q2, Q3.
不是 Q1、Q2、Q3。 With that modification, I wrote this code:
通过该修改,我编写了以下代码:
module verilogtest(clk, CS, q, clr);
input clk, CS, clr;
output[3:0] q;
counter count(clk, CS, q, clr);
endmodule
module counter(clk, CS, q, clr);
input clk, CS, clr;
output[3:0] q;
wire t1, t2, t3;
assign #1
t1 = CS & q[0],
t2 = t1 & q[1],
t3 = t2 & q[2];
mJKff ff1(q[0], CS, CS, clk, clr);
mJKff ff2(q[1], t1, t1, clk, clr);
mJKff ff3(q[2], t2, t2, clk, clr);
mJKff ff4(q[3], t3, t3, clk, clr);
endmodule
module mJKff(Q, J, K, clk, clr);
output Q;
input J, K, clk, clr;
wire
a, b, c, d, y, ybar, cbar, qbar;
assign #1
a = ~(qbar & J & clk & clr),
b = ~(clk & K & Q),
y = ~(a & ybar),
ybar = ~(y & clr & b),
c = ~(y & cbar),
d = ~(ybar & cbar),
cbar = ~clk;
assign #1
qbar = ~(Q & clr & d),
Q = ~(c & qbar);
endmodule
I compile successfully with Quartus II and get a bunch of warnings:我使用 Quartus II 成功编译并收到一堆警告:
Warning: Timing Analysis is analyzing one or more combinational loops as latches
警告:时序分析正在将一个或多个组合循环分析为锁存器
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
警告:未指定保留所有未使用的引脚设置,将默认为“作为输出驱动接地”。
Warning: Found pins functioning as undefined clocks and/or memory enables
警告:发现引脚用作未定义的时钟和/或内存启用
Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
警告:在时钟路径中发现 7 个节点,它们可能充当纹波和/或门控时钟——节点被分析为导致时钟偏移的缓冲器
Warning: Circuit may not operate.
警告:电路可能无法运行。 Detected 2 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay.
检测到由时钟“clk”计时的 2 个非操作路径,其时钟偏差大于数据延迟。 See Compilation Report for details.
有关详细信息,请参阅编译报告。
Warning: Circuit may not operate.
警告:电路可能无法运行。 Detected 1 non-operational path(s) clocked by clock "CS" with clock skew larger than data delay.
检测到由时钟“CS”计时的 1 个非操作路径,其时钟偏差大于数据延迟。 See Compilation Report for details.
有关详细信息,请参阅编译报告。
Warning: Circuit may not operate.
警告:电路可能无法运行。 Detected 1 non-operational path(s) clocked by clock "clr" with clock skew larger than data delay.
检测到 1 个由时钟“clr”计时的非操作路径,其时钟偏差大于数据延迟。 See Compilation Report for details.
有关详细信息,请参阅编译报告。
I think the last 3 warning is the reasons why it doesn't work.我认为最后 3 个警告是它不起作用的原因。 Simulation result:
模拟结果:
Q0 behaves as expected, but the rest is not. Q0 的行为符合预期,但其余的则不然。 Why?
为什么?
You just have a simple error in wiring the AND gates in your counter module:您只是在计数器模块中连接与门时遇到了一个简单的错误:
assign #1
t1 = CS & q[0],
t2 = t1 & q[1],
t3 = t2 & q[2];
should be应该
assign #1
t1 = CS & q[1],
t2 = t1 & q[2],
t3 = t2 & q[3];
Q[0]
is the only output behaving correctly because the JK inputs of all the other FFs are receiving the wrong values. Q[0]
是唯一行为正确的输出,因为所有其他 FF 的 JK 输入都接收到错误的值。
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