Verilog 对具有同步复位 (R) 的边沿触发 T 触发器的结构描述

Question

I am trying to wire a Verilog Structural description of an Edge-triggered T flip-flop with an synchronous reset (R). Here is the circuit for this element:

Now assume that I have already written the behavioral description for each block in this schematic, so here is my structural description for this circuit by instantiation of each of this blocks in the circuit:

    module edge_trig_flipflop_structure (
input x,y,clk,
  output q,
  wire a,b,c,d
);
  inv u1(c,q);
  mux_2x1 u2 (q,c,x,a);
  inv u3(d,y);
  and_2_1 u4(b,a,d);
  d_flipflop u5(b,clk,q);
endmodule

Is this a good efficient code for this circuit? In other words, do I really need the two extra wires used for the inverters which are the wires c and d Or, is there another efficient way to write this code?

Edit: Here is the code for each component to know the order of ports in the declaration of each component

module mux_2x1 (
input a,
input b,
input sel,
output reg c
);
 
  always @ (*) begin 
    case ( sel)
      1'b0: c=a;
      1'b1: c=b;
      default : $dispaly ("error");
   endcase
 end
        
  
endmodule 

module d_flipflop ( input d,clk , output reg q);

 always @ (posedge clk ) begin
   q=d;
      
  end 
  
endmodule
module inv(output reg b, input a);
  
  always @ (a) begin 
    b=~a;
  
  
  
  end
  
endmodule

module and_2_1 ( output reg c,input a,b);

always @(a or b) begin 
  if (a==1'b1 & b==1'b1)
    c= 1'b1;
  else
    c=1'b0;
  

end

endmodule

Answer 1

By default, Verilog does not require you to declare all signals. If signals appear in port connections, they will implicitly be 1-bit wire types.

However, it is good practice to declare all signals explicitly with wire , as you have done.

You could also change the default behavior and require explicitly declared signals using this compiler directive:

`default_nettype none

---

Since you are also concerned about connections, it is a good practice to make connections by name instead of connections by position. It is more verbose, but it will help avoid simple connection errors. For example:

  inv u1 (.b(c), .a(q));

---

I got compile errors on your module header. You probably meant to code it this way:

module edge_trig_flipflop_structure (
  input x,y,clk,
  output q
);

  wire a,b,c,d;