使用 D 触发器的 4 位寄存器，具有启用和异步复位功能

Question

I am modelling a 4-bit register using D flip-flops with enable and asynchronous reset. It contains 4 D FF and 4 2:1 Mux. I used structural Verilog to model the circuit.

My design is shown below.

module DFlipFlop(D,clk,reset,Q);
input D; 
input clk,reset; 
output Q;
reg Q;
always @(posedge clk or posedge reset) 
begin
 if(reset==1'b1)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule

module m21(D0, D1, S, Y);
output Y;
input D0, D1, S;
assign Y=(S)?D1:D0;
endmodule

module DFF_with_Enable(D,clk,enable,reset,Q);
  input D,clk,reset,enable;
  output Q;
  reg Q;
  wire in;
      m21 mux(D,in,enable,in);
      DFlipFlop DFF(in,clk,reset,Q); 
endmodule

module fourbitreg(D,clk,reset,enable, Q);
  input[0:3] D; // Data input
input clk,reset,enable;
  output [3:0]Q;
  reg [3:0]Q;
  wire d0,d1,d2,d3;
  wire q0,q1,q2,q3;
  d0 = D[0];
  d1 = D[1];
  d2 = D[2];
  d3 = D[3];
  DFF_with_Enable df0(d0,clk,reset,enable,q0);
  DFF_with_Enable df1(d1,clk,reset,enable,q1);
  DFF_with_Enable df2(d2,clk,reset,enable,q2);
  DFF_with_Enable df3(d3,clk,reset,enable,q3);
        
       assign Q = {q0,q1,q2,q3};
endmodule

I used iverilog for simulation. How do I fix the following errors during compilation?

design.sv:37: syntax error
design.sv:37: error: Invalid module instantiation
design.sv:38: error: Invalid module instantiation
design.sv:39: error: Invalid module instantiation
design.sv:40: error: Invalid module instantiation

The circuit of 1 DFF MUX pair is shown below.

Answer 1

There are multiple compile errors.

Inside DFF_with_Enable and fourbitreg , do not declare Q as a reg because you make continuous assignments to Q .

You need to use the assign keyword to make continuous assignments to d0 , etc.:

  assign d0 = D[0];
  assign d1 = D[1];
  assign d2 = D[2];
  assign d3 = D[3];

You should also try different simulators on edaplayground to get more meaningful error messages.