[英]Output of D flip-flop not as expected
It is async reset.它是异步重置。 D flipflop when i change reset from one to zero, it doesn't immediately raise the output from zero to one. D触发器当我将复位从一更改为零时,它不会立即将输出从零提高到一。 but when i add in @always ( posedge clk or posedge reset or negedge reset ) it immediately change但是当我添加@always(posedge clk 或 posedge reset 或 negedge reset )时,它会立即改变
module dff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset)
begin
if (reset)
q =0;
else
q <= data;
end
endmodule //End Of Module dff_async_reset
It does exactly what you tell it to do: mimic a flip-flop with an asynchronous active-high reset.它完全按照您的要求执行:模仿具有异步高电平有效复位的触发器。 The following line from your code您的代码中的以下行
always @ (posedge clk or posedge reset)
says: "execute this procedural block when clk
makes the transition 0 --> 1
or when reset
makes the transition 0 --> 1
."说:“当clk
进行转换0 --> 1
或reset
进行转换0 --> 1
时执行此程序块。” In other words, when reset
makes the transition 1 --> 0
, this always block will not be evaluated.换句话说,当reset
进行转换1 --> 0
时,将不会评估这个 always 块。
You value q
will only be updated on the positive edge of clk
, which is exactly what you want if you want to design a flip-flop.您的价值q
只会在clk
的上升沿更新,如果您想设计一个触发器,这正是您想要的。
When you add negedge reset
to your sensitivity list, it will indeed immediatelly change when you go out of your reset state (which is 1 --> 0
in your logic).当您将negedge reset
添加到您的敏感度列表中时,当您退出重置状态(在您的逻辑中为1 --> 0
)时,它确实会立即改变。 This is, however, usually not desired.然而,这通常是不希望的。 Rather, you should synchronize the deassertion of your reset to your clock signal .相反, 您应该将复位的取消断言与时钟信号同步。 To quote from the aforementioned website:引用上述网站:
The way most of the designs have been modelled needs asynchronous reset assertion and synchronous de-assertion.大多数设计的建模方式需要异步复位断言和同步解除断言。 The requirement of most of the designs these days is:如今,大多数设计的要求是:
- When reset is asserted, it propagates to all designs;当复位被断言时,它会传播到所有设计; brings them to reset state whether or not clock is toggling;无论时钟是否切换,都使它们进入重置状态; ie assertion should be asynchronous即断言应该是异步的
- When reset is deasserted, wait for a clock edge, and then, move the system to next state as per the FSM (Finite State Machine);当复位无效时,等待时钟沿,然后根据 FSM(有限状态机)将系统移动到下一个状态; ie deassertion should be synchronous即取消断言应该是同步的
module PRVO_SLOVO_IMENA(output x,input a,b);模块 PRVO_SLOVO_IMENA(输出 x,输入 a,b);
assign x=a&b;
endmodule端模块
module DRUGO_SLOVO_IMENA(output x,input a,b);模块 DRUGO_SLOVO_IMENA(输出 x,输入 a,b);
assign x=a|b;
endmodule端模块
module TRECE_SLOVO_IMENA(output x,input a,b);模块 TRCE_SLOVO_IMENA(输出 x,输入 a,b);
assign x=a^b;
endmodule端模块
module PREZIME(output y, input a,b,c,d);模块 PREZIME(输出 y,输入 a,b,c,d);
reg mand,mxor;
TRECE_SLOVO_IMENA o1(.x(mxor),.a(a),.b(b));
PRVO_SLOVO_IMENA o2(.x(mand),.a(mxor),.b(c));
DRUGO_SLOVO_IMENA o3(.x(y),.a(mand),.b(d));
endmodule端模块
module dff(data, clk, reset, q
);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end
else begin
q <= data;
end
endmodule
module registar_IME(input clk, reset, [7:0] in, output [7:0] q);
dff dff_1(.data(in[7]), .clk(clk), .reset(reset), .q(q[7]));
dff dff_2(.data(in[6]), .clk(clk), .reset(reset), .q(q[6]));
dff dff_3(.data(in[5]), .clk(clk), .reset(reset), .q(q[5]));
dff dff_4(.data(in[4]), .clk(clk), .reset(reset), .q(q[4]));
dff dff_5(.data(in[3]), .clk(clk), .reset(reset), .q(q[3]));
dff dff_6(.data(in[2]), .clk(clk), .reset(reset), .q(q[2]));
dff dff_7(.data(in[1]), .clk(clk), .reset(reset), .q(q[1]));
dff dff_8(.data(in[0]), .clk(clk), .reset(reset), .q(q[0]));
endmodule
module registar_PREZIME(input clk, reset, [7:0] in, output [7:0] q);
dff dff_1(.data(in[7]), .clk(clk), .reset(reset), .q(q[7]));
dff dff_2(.data(in[6]), .clk(clk), .reset(reset), .q(q[6]));
dff dff_3(.data(in[5]), .clk(clk), .reset(reset), .q(q[5]));
dff dff_4(.data(in[4]), .clk(clk), .reset(reset), .q(q[4]));
dff dff_5(.data(in[3]), .clk(clk), .reset(reset), .q(q[3]));
dff dff_6(.data(in[2]), .clk(clk), .reset(reset), .q(q[2]));
dff dff_7(.data(in[1]), .clk(clk), .reset(reset), .q(q[1]));
dff dff_8(.data(in[0]), .clk(clk), .reset(reset), .q(q[0]));
endmodule
module DRUGI_ZADATAK(input clk, reset, [7:0] in, output [7:0] q
);
registar_IME r_IME(.clk(clk), .reset(reset),
.in(KOPIRAJ_SVOJE_IZ_KOMENTARA), .q(prvi));//OBRISI KAD KOPIRAS poki
1'b1011010 vlada 1'b110111 sveta 1'b1000110
registar_PREZIME r_PREZIME(.clk(clk), .reset(reset), .in(1'b101101),
.q(drugi));
endmodule
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