[英]JK Flip-flop using D Flip-flop and gate level simulation does not stop
I'm trying to implement a JK flip-flop with a D flip-flop and a gate level, but the problem is that when I run the code, the terminal doesn't show me anything.我正在尝试使用 D 触发器和门级实现 JK 触发器,但问题是当我运行代码时,终端没有显示任何内容。 It's like it has always been calculating but nothing is shown.
就好像它一直在计算,但什么也没显示。 I need to press
crtl + c
to stop the process, and this is when cmd shows something, but it is not the complete result.我需要按
crtl + c
停止该过程,这是 cmd 显示某些内容的时候,但这不是完整的结果。 I attached my code and images of the cmd.我附上了我的 cmd 代码和图像。
module D_flip_flop (input D,clk,Reset,enable,output reg F);
always @(*)
begin
if (Reset)
F<='b0;
else if (enable && clk)
F<=D;
end
endmodule
module JK_flip_flop(input J,K,clk,Reset,enable,output Q);
wire S1,S2,S3,S4,S5;
D_flip_flop D1(S4,clk,Reset,enable,Q);
not N2(S5,Q);
and A1(S1,J,S5);
not N1(S3,K);
and A2(S2,S3,Q);
or O1(S4,S1,S2);
endmodule
testbench:试验台:
module testbench();
reg clk,reset,enable,J,K;
wire Q;
JK_flip_flop J1(J,K,clk,reset,enable,Q);
initial begin
$display("\n");
$display("Flip Flop JK");
$display("J K clk Reset Enable | Q ");
$display("----------------|---");
$monitor("%b %b %b %b %b | %b", J,K,clk,reset,enable,Q);
J=0;K=0;reset=1;enable=0;clk=0;
#1 reset=0;enable=1;
#10 J=0;K=1;
#10 J=1;K=0;
#10 J=0;K=1;
#10 J=1;K=1;
#10 J=0;K=0;
#50 $finish;
end
always
begin
#5 clk =~clk;
end
initial begin
$dumpfile("Ej3_tb.vcd");
$dumpvars(0, testbench);
end
endmodule
Terminal before top the process:顶进程前的终端:
Terminal after stop Process:停止后的终端过程:
The JK flip-flop i'm trying to implement:我正在尝试实现的 JK 触发器:
I don't know why this happening.我不知道为什么会这样。
That is an incorrect way to model a DFF in Verilog.这是在 Verilog 中对 DFF 建模的错误方法。 This is the recommended way, triggering off the rising edge of the clock:
这是推荐的方式,触发时钟的上升沿:
module D_flip_flop (input D,clk,Reset,enable, output reg F);
always @(posedge clk) begin
if (Reset)
F <= 1'b0;
else if (enable)
F <= D;
end
endmodule
The above code uses a synchronous reset.上面的代码使用了同步复位。
This change allows the simulation to terminate cleanly (without a Ctrl-C
).此更改允许模拟干净地终止(没有
Ctrl-C
)。
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