在 Verilog 中使用门级描述的 JK 触发器给我一个时序错误

Question

I still playing in the lowest Verilog level (gate level). I found this post: https://electronics.stackexchange.com/questions/390661/is-it-possible-to-create-a-working-jk-flip-flop-using-gate-level-description-in in that I could understand that shoud work the idea, and I could solve to have a Master-Slave JK Flip-Flop for use it as a frequency divider. I use Icestorm toolchain, Yosys is not complaining, but Next-PNR is giving me this error:

ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.

This is my code:

module syncRX(clk, signal, detect);
    output wire [7:0] detect;
    input clk, signal;
    
    reg [6:0] det = 7'b1001010;
    
    assign detect = {det, jk5_out};
    
    jk_flip_flop_edge_triggered jk0(.Q(jk5_out), .Qn(Qn), .C(clk), .J(1), .K(1), .RESETn(0));

endmodule // top

module jk_flip_flop_edge_triggered(Q, Qn, C, J, K, RESETn);
   output Q;
   output Qn;
   input  C;
   input  J;
   input  K;
   input  RESETn;

   wire   Kn;   // The complement of the K input.
   wire   D;   
   wire   D1;   // Data input to the D latch.   
   wire   Cn;   // Control input to the D latch.
   wire   Cnn;  // Control input to the SR latch.
   wire   DQ;   // Output from the D latch, inputs to the gated SR latch (S).
   wire   DQn;  // Output from the D latch, inputs to the gated SR latch (R).

   assign D1 = !RESETn ? 0 : D;  // Upon reset force D1 = 0

   not(Kn, K);   
   and(J1, J, Qn);
   and(K1, Kn, Q);   
   or(D, J1, K1);   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D1);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule

module d_latch(Q, Qn, G, D);
   output Q;
   output Qn;
   input  G;   
   input  D;

   wire   Dn; 
   wire   D1;
   wire   Dn1;

   not(Dn, D);   
   and(D1, G, D);
   and(Dn1, G, Dn);   
   nor(Qn, D1, Q);
   nor(Q, Dn1, Qn);
endmodule

module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;

   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule

Well, I can imagine the answer if I ask what happends, I would like to know why and how make it works! Thanks to all!

Answer 1

Loops:

pin syncRX.jk0.dl.D --> pins syncRX.jk0.dl.Q/Qn --> pins syncRX.jk0.sr.S/R --> pins syncRX.jk0.sr.Q/Qn --> pin syncRX.jk0.dl.D

If you instantiate latch cell from standard library, issues related to timing path and timing check will be handled by that cell.

I would certainly think the loop will be reported by every well-known implementation tool. But since you said Yosys is not complaining, I'm also confused (I haven't used Yosys.)