如何从凿子解读生成的Verilog中的注释？

Question

Here is some genereated Verilog from the PassTrough module found in: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb

module PassTrough( // @[:@3.2]
  input        clock, // @[:@4.4]
  input        reset, // @[:@5.4]
  input  [9:0] io_in, // @[:@6.4]
  output [9:0] io_out // @[:@6.4]
);
  assign io_out = io_in; // @[buffer.scala 10:10:@8.4]
endmodule

Are there any resources about understanding what is in the comments. I can see that they related to the code location in the original scala file but would like to know more details.

// @[buffer.scala 10:10:@8.4]

A more detailed explanation of this line would be useful.

Answer 1

These are source locators and will show up in generated FIRRTL or Verilog. These tell you what line in a source file (Chisel or FIRRTL) was used to generate a specific line in the downstream FIRRTL or Verilog.

The format is generally: @[<file> <line>:<column> ...]

More than one source locator may be present.

Example

Consider the following example pulled from the BoringUtilsSpec . The line numbers (which do not start at zero as this was extracted from a larger file) are shown along with the column numbers. You can see how things line up between them. For example, the declaration of notA happens on line 27 column 20 and the assignment notA := ~a happens on line 30, column 10. You see 27:20 and 30:10 show up in the FIRRTL. In the Verilog, these get merged somewhat and you wind up with source locators indicating both 27:20 and 30:10 :

// -------------------------------------------+----+
// File: BoringUtilsSpec.scala                |    |
// -------------------------------------------+----+
// Column Number                              |    |
// -------------------------------------------+----+
//           1         2         3         4  |    |
// 01234567890123456789012345678901234567890  |    |
// -------------------------------------------+----|
     class BoringInverter extends Module { // | 24 | Line Number
       val io = IO(new Bundle{})           // |  5 |
       val a = Wire(UInt(1.W))             // |  6 |
       val notA = Wire(UInt(1.W))          // |  7 |
       val b = Wire(UInt(1.W))             // |  8 |
       a := 0.U                            // |  9 |
       notA := ~a                          // | 30 |
       b := a                              // |  1 |
       chisel3.assert(b === 1.U)           // |  2 |
       BoringUtils.addSource(notA, "x")    // |  3 |
       BoringUtils.addSink(b, "x")         // |  4 |
     }                                     // |  5 |
// -------------------------------------------+----+

This produces the following FIRRTL:

module BoringUtilsSpecBoringInverter : 
  input clock : Clock
  input reset : UInt<1>
  output io : {}

  wire a : UInt<1> @[BoringUtilsSpec.scala 26:17]
  wire notA : UInt<1> @[BoringUtilsSpec.scala 27:20]
  wire b : UInt<1> @[BoringUtilsSpec.scala 28:17]
  a <= UInt<1>("h00") @[BoringUtilsSpec.scala 29:7]
  node _T = not(a) @[BoringUtilsSpec.scala 30:13]
  notA <= _T @[BoringUtilsSpec.scala 30:10]
  b <= a @[BoringUtilsSpec.scala 31:7]
  node _T_1 = eq(b, UInt<1>("h01")) @[BoringUtilsSpec.scala 32:22]
  node _T_2 = bits(reset, 0, 0) @[BoringUtilsSpec.scala 32:19]
  node _T_3 = or(_T_1, _T_2) @[BoringUtilsSpec.scala 32:19]
  node _T_4 = eq(_T_3, UInt<1>("h00")) @[BoringUtilsSpec.scala 32:19]
  // assert not shown

And the following Verilog:

module BoringUtilsSpecBoringInverter(
  input   clock,
  input   reset
);
  wire  _T; // @[BoringUtilsSpec.scala 30:13]
  wire  notA; // @[BoringUtilsSpec.scala 27:20 BoringUtilsSpec.scala 30:10]
  wire  _T_3; // @[BoringUtilsSpec.scala 32:19]
  wire  _T_4; // @[BoringUtilsSpec.scala 32:19]
  assign _T = 1'h1; // @[BoringUtilsSpec.scala 30:13]
  assign notA = 1'h1; // @[BoringUtilsSpec.scala 27:20 BoringUtilsSpec.scala 30:10]
  assign _T_3 = _T | reset; // @[BoringUtilsSpec.scala 32:19]
  assign _T_4 = _T_3 == 1'h0; // @[BoringUtilsSpec.scala 32:19]
  // assert not shown
endmodule

Caveats

Generator Bootcamp

If you are running this in the Chisel Bootcamp Jupyter Notebook or through an sbt console/REPL, the source locators may not make as much sense as there really isn't a file here with lines.

Difference with Annotation

These source locators are not Annotation s, in case anyone has come across that name.

Annotation s are metadata associated with circuit components. Source locators (which map to Info in the FIRRTL IR) are associated with specific statements in some source file. Under the hood they're just strings that get generated and then copied around. There is no guarantee that source locators will be preserved---they may be changed or deleted arbitrarily. Conversely, Annotation s are preserved and renamed across transformations and have strong guarantees on how they behave.

Consequently, do not rely on source locators for anything other than an aid if you need to debug the Chisel or FIRRTL compiler stages.