在chisel中，如何判断一个模块的Bundle是否实际生成为verilog

Question

In chisel, If I define the bundle of a module like this.

class tmp extends Module{
  val io  = IO(new Bundle  {
    val enable = Input(Bool())
    val data = Input(UInt(4.W))
    val out = Output(UInt(4.W))
    val tmp = Output(UInt(32.W))
  })
  io.out := RegEnable(io.data, io.enable)
  io.tmp := RegEnable(!io.data, io.enable)
}

Then I call it in the upper module

class q extends Module{
  val io  = IO(new Bundle{
    val in = Input(UInt(4.W))
    val out = Output(UInt(32.W))
})
  val q = Module(new tmp)
  q.io.enable := true
  q.io.data := io.in
  io.out := q.io.out
}

the tmp bundle of the tmp module will not be generated as verilog. How do I know that bundles like tmp are not generated without looking at verilog.

Answer 1

This is because of the way your code is written. You essentially just created another class to send in inputs and receive the output of the tmp module. Therefore Chisel optimizes the inputs and output of tmp to a bunch of wires which are being driven by the input and output pins of q module. If you want to keep the tmp module then I would suggest you to not drive the io pins of the module from any other class. Rather just keep it that way and once the verilog is generated you can write a testbench to drive the io pins of tmp module.