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如何在 Chisel 中初始化一个 Reg of Bundle?

[英]How to initialize a Reg of Bundle in Chisel?

I declared a Bundle for my specific data :我为我的特定数据声明了一个 Bundle :

class RValue (val cSize: Int = 16) extends Bundle {
  val rvalue = Output(UInt(cSize.W))
  val er     = Output(UInt((cSize/2).W))
  val part   = Output(Bool()) /* set if value is partial */
}

And I want to use it as a register in my module :我想将它用作我模块中的寄存器:

  val valueReg = Reg(new RValue(cSize))
//...
  valueReg.rvalue := 0.U
  valueReg.er := 0.U

That works well.这很好用。 But I want to initialize it at Register declaration with RegInit().但我想在注册声明中使用 RegInit() 对其进行初始化。 Is it Possible ?是否可以 ?

  val valueReg = RegInit(new RValue(cSize), ?? ) ??

Chick's answer of using Bundle Literals is the cool new way and is nice because you can give a Bundle arbitrary values in a single expression. Chick 对使用 Bundle Literals 的回答是一种很酷的新方法,而且很好,因为您可以在单个表达式中为 Bundle 提供任意值。

If you just want to zero-out the register at reset type, you could always cast from a literal zero to the Bundle:如果您只想在复位类型将寄存器清零,您始终可以从文字零转换为 Bundle:

val valueReg = RegInit(0.U.asTypeOf(new RValue(cSize))

You can do similar things with any literal if you want, but I wouldn't recommend it unless you're zeroing out or setting everything to 1s.如果你愿意,你可以用任何文字做类似的事情,但我不会推荐它,除非你将所有内容归零或设置为 1。

For setting each field to some other value, I think Chick's way is better, but the normal style you'll see in older code is something like:为了将每个字段设置为其他值,我认为 Chick 的方式更好,但是您在旧代码中会看到的正常样式类似于:

val valueReg = RegInit({
  val bundle = Wire(new RValue(cSize))
  bundle.rvalue := 1.U
  bundle.er := 2.U
  bundle.part := 3.U
  bundle
})

In Scala, you can put { } anywhere an expression is needed and the last expression in the Block will be the return value.在 Scala 中,您可以将{ }放在需要表达式的任何位置,块中的最后一个表达式将是返回值。 Thus we can create a Wire with the values we want to reset the register to and then pass that Bundle as the initialization value.因此,我们可以使用我们想要将寄存器重置为的值创建一个 Wire,然后将该 Bundle 作为初始化值传递。 It would be equivalent to write:这相当于写:

val valueRegInit = Wire(new RValue(cSize))
valueRegInit.rvalue := 1.U
valueRegInit.er := 2.U
valueRegInit.part := 3.U
val valueReg = RegInit(valueRegInit)

I hope this helps!我希望这有帮助!

BundleLiterals are the new way to do this. BundleLiterals 是实现此目的的新方法。 First第一的

import chisel3.experimental.BundleLiterals._

Then然后

val valueReg = RegInit((new RValue(cSize)).Lit(_.rvalue -> 1.U, _.er -> 2.U, _.part -> true.B)

It's possible there will be some problem with having declared the fields in the Bundle with the OutputBinding.使用 OutputBinding 在 Bundle 中声明字段可能会出现一些问题。 I would probably leave that off and just wrap with the output when necessary, eg我可能会离开它,并在必要时用输出包装,例如

val rValueOut = IO(Output(new RValue(csize)))

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