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如何在Chisel中初始化ShiftRegister原语

[英]How to initialize ShiftRegister primitive in Chisel

We are using ShiftRegister in Chisel 2 to implement a delay. 我们在凿子2中使用ShiftRegister来实现延迟。 But it's not clear how to force it to initialize to a value of our choosing, such as forcing it to zero (NOT random). 但是尚不清楚如何强制将其初始化为我们选择的值,例如将其强制为零(不是随机的)。 How to do this? 这个怎么做?

I have not much with Chisel 2, but I believe this ShiftRegister.apply method should work. 我对Chisel 2的了解不多,但是我相信ShiftRegister.apply方法应该可以工作。

In Chisel 3, there is an open PR to add this functionality. 在Chisel 3中,有一个开放的PR可以添加此功能。 Without this PR, it is still possible as follows: 没有此PR,仍然可能如下:

val shiftIn = Wire(UInt(32.W))
val shiftReg = ShiftRegister(Mux(reset, RESET_VALUE, shiftIn), n)

Just connect to shiftIn to input to the shiftReg. 只需连接到shiftIn即可输入shiftIn

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