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如何在VCS中测试Chisel生成的verilog模块？ vpi_uer.cc如何在凿子中工作？

[英]How to test the verilog module generated by Chisel in VCS ? How does vpi_uer.cc work in chisel?

原文 2015-07-16 03:01:23 2 1 chisel

In chisel-tutorial ,after I ran 在凿子教程中，我跑了之后

sbt "run Hello --backend v --compile --test --genHarness --vcd"

I got the Hello.v ,Hello-harness.v ,vpi_user.cc files 我得到了Hello.v，Hello-harness.v，vpi_user.cc文件

How can I test the Hello.v file? 如何测试Hello.v文件？
What is the usage of vpi_user.cc? vpi_user.cc的用途是什么？

1 个解决方案

To test your design in VCS you can use the two verilog files generated: 要在VCS中测试设计，可以使用生成的两个Verilog文件：

Hello.v : Your Chisel design generated in Verilog Hello.v：您在Verilog中生成的凿子设计
Hello-harness.v : Your testbench code in Verilog (generated by --genHarness option). Hello-harness.v：您在Verilog中的测试平台代码（由--genHarness选项生成）。 Of course you have to modify it to improve your test. 当然，您必须对其进行修改以改善您的测试。

在chisel中，如何判断一个模块的Bundle是否实际生成为verilog - In chisel, how to judge whether the Bundle of a module is actually generated as a verilog

如何从凿子解读生成的Verilog中的注释？ - How to decipher comments in generated Verilog from chisel?

如何在生成的 Verilog 中使用 chisel Vector 中所选元素的 val 名称 - How to to use the val name of selected element in a chisel Vector in the generated Verilog

是否有一个如何从 Chisel3 模块生成 verilog 的简单示例？ - Is there a simple example of how to generate verilog from Chisel3 module?

如何在Chisel3中添加verilog综合指令？ - How to add verilog synthesis directives in Chisel3?

为什么除了chisel生成的ProgramCounter之外没有其他模块的verilog代码？ - Why there is no verilog code of other module except ProgramCounter generated by chisel?

在凿子中，如何生成具有不同参数的伺服模块？ - In chisel, How to generate serval Module with different parameter?

Chisel3：如何同时获取verilog，cpp和vcd文件 - Chisel3: How to get verilog,cpp and vcd files simultaneously

chisel 中如何解释这种语法？ - How is this syntax explained in chisel?

凿子如何测试只有一个package - Chisel how to test only one package

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