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在使用 Icarus 模拟 verilog output 时，有没有办法在模拟中包含 RAM 等 FPGA 硬件特性？

[英]When simulating verilog output using Icarus, is there a way to include FPGA hardware features such as RAM in the simulation?

原文 2022-01-17 03:13:10 3 1 verilog/ simulation/ fpga/ icarus

I'm new to FPGA, and have started out with an iceBreaker board using the ICE40UP5K chip.我是 FPGA 新手，并且开始使用使用 ICE40UP5K 芯片的 iceBreaker 板。 I'm aiming to make a LED display driver, driving something similar to HUB75 used on popular display modules.我的目标是制作一个 LED 显示驱动器，驱动类似于流行显示模块上使用的 HUB75 的东西。

I've been able to simulate waveform generation, and view it in GtkWave using the tutorial here: https://brng.dev/blog/technical/tutorial/2019/05/11/icarus_gtkwave/我已经能够模拟波形生成，并使用此处的教程在 GtkWave 中查看它： https://brng.dev/blog/technical/tutorial/2019/05/11/icarus_gtkwave/

My next steps involve making use of the RAM banks inside of the ICE40UP5K.我接下来的步骤涉及使用 ICE40UP5K 内部的 RAM 组。 Is there some way to include the existence of this RAM in my simulation?有没有办法在我的模拟中包含这个 RAM 的存在？

1 个解决方案

Yes, of course - there is a library of simulated ICE40 cells included in Yosys: https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v是的，当然 - Yosys 中包含一个模拟 ICE40 单元库： https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v

使用Icarus Verilog模拟程序计数器设计时出现无限循环 - Infinite loop when simulating a Program Counter design with Icarus Verilog

如何在icarus verilog中包括文件？ - How to include files in icarus verilog?

使用仿真和使用 FPGA 计算处理时间 Verilog - Compute processing time Verilog using simulation and using FPGA

FPGA（Verilog）-在仿真中工作，但在FPGA上不工作 - FPGA (Verilog) - Working in simulation but not working on FPGA

Icarus Verilog仿真：范围索引表达式不是常数： - Icarus Verilog simulation : Scope index expression is not constant: i

Verilog：uart关于FPGA和仿真行为的差异 - Verilog : uart on FPGA and simulation behavioural differences

Verilog代码在Simulation中工作得很好，但在FPGA上却不能 - Verilog code works very well in Simulation but not on FPGA

Verilog：仿真出错但在 FPGA 上运行良好 - Verilog: simulation gives errors but runs fine on FPGA

让FPGA使用verilog在“ line out”引脚上输出声音 - Having FPGA to output sound on “line out” pin using verilog

当我在Xilinx中使用Verilog描述硬件RAM时，如何解决警告“ HDLCompiler：1007-进入memp的元素索引7超出范围”？ - How can I fix the warning “ HDLCompiler: 1007 - Element index 7 into memp is out of bounds” when I describe the hardware RAM, using Verilog in Xilinx?

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