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When simulating verilog output using Icarus, is there a way to include FPGA hardware features such as RAM in the simulation?

原文 2022-01-17 03:13:10 5 1 verilog/ simulation/ fpga/ icarus

I'm new to FPGA, and have started out with an iceBreaker board using the ICE40UP5K chip. I'm aiming to make a LED display driver, driving something similar to HUB75 used on popular display modules.

I've been able to simulate waveform generation, and view it in GtkWave using the tutorial here: https://brng.dev/blog/technical/tutorial/2019/05/11/icarus_gtkwave/

My next steps involve making use of the RAM banks inside of the ICE40UP5K. Is there some way to include the existence of this RAM in my simulation?

1 answers

Yes, of course - there is a library of simulated ICE40 cells included in Yosys: https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v

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When simulating verilog output using Icarus, is there a way to include FPGA hardware features such as RAM in the simulation?

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solution1 0 2022-01-25 09:10:25

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0 2022-01-25 09:10:25