[英]How do I code a basic flip flop in Verilog Pro?
I tried to code a basic flip flop using NAND gates in Verilog Pro, but the waveform I'm getting is not correct. 我试图在Verilog Pro中使用“与非”门对基本触发器进行编码,但是获得的波形不正确。 Please see what's wrong with it. 请看看有什么问题。
//design module
module rstt(s,r,q,qbar);
input r,s;
output q,qbar;
nand n1(q,r,qbar);
nand n2(qbar,s,q);
endmodule
//stimulus module
module test;
reg r,s;
wire q,qbar;
initial begin
r=1'b1;
s=1'b0;
#25 r=1'b0;
s=1'b1;
#25 r=1'b1;
s=1'b1;
#100 $finish;
end
endmodule
You did not instantiate your rstt
module inside your test
module. 您没有在test
模块中实例化rstt
模块。 This means that the wires ( q
and qbar
) inside module test
are undriven. 这意味着模块test
中的导线( q
和qbar
)是未驱动的。 That is why they remain as straight lines instead of toggling. 这就是为什么它们保持直线而不是切换的原因。 According to the IEEE Verilog standard, a undriven wire
will default to 1'bz
. 根据IEEE Verilog标准,未驱动的wire
将默认为1'bz
。
Try something like this: 尝试这样的事情:
//design module
module rstt(s,r,q,qbar);
input r,s;
output q,qbar;
nand n1(q,r,qbar);
nand n2(qbar,s,q);
endmodule
//stimulus module
module test;
reg r,s;
wire q,qbar;
rstt i0 (
.s (s),
.r (r),
.q (q),
.qbar (qbar)
);
initial begin
r=1'b1;
s=1'b0;
#25 r=1'b0;
s=1'b1;
#25 r=1'b1;
s=1'b1;
#100 $finish;
end
endmodule
Note that your problem is not specific to any simulator. 请注意,您的问题并非特定于任何模拟器。
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