如何使用系统verilog设计一个在2个时钟周期后对输入进行采样的触发器？

Question

the data is input in the first posedge clock but the output should present after 2 clock cycles.

i've tried using #delay but not quite getting it.

clk=0;
forever #10 clk = ~clk;
always @ (posedge clk) begin //synchronous rst
#60 q<=d;
end

Answer 1

One way to solve your problem would be to have 2 flip-flops.

reg q1, q2;
always @(posedge clk) begin
   q1 <= d;
   q2 <= q1;
end

Now, q2 will follow the input with a 2 clock-cycle latency, which is what you wanted.