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我怎么知道我的代码是否是Synthesizable？ [Verilog的]

[英]how can i know if my code is Synthesizable? [Verilog]

原文 2011-09-27 06:34:04 8 2 verilog/ hdl

In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. 在使用自顶向下方法设计verilog电路时，我可以从电路的行为开始，然后在每个模块中定义细节，以构建可合成的结构电路。 But how can I know if my code is synthesizable? 但是我怎么知道我的代码是否可以合成？ Are there any guidelines to follow to support synthesis in verilog? 在verilog中是否有任何指导可用于支持综合？

2 个解决方案

There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. 有一个'标准'， IEEE 1364.1，但Martin指出每个工具都支持它想要的任何东西。 I recommend the Xilinx XST User Guide if you need a free resource. 如果您需要免费资源，我推荐使用Xilinx XST用户指南。

Also, structural verilog typically means you are creating description close to a netlist and the constructs you would use in this case are a small subset of those that are synthesizable. 此外，结构verilog通常意味着您创建接近网表的描述，并且在这种情况下您将使用的构造是可合成的构造的一小部分。

Read the documentation that comes with whatever synthesis tool you are going to be using. 阅读您将要使用的任何综合工具附带的文档。 This will show you what you can do - sometimes there are very specific ways you have to write code to get the intended results. 这将向您展示您可以做什么 - 有时您需要编写代码才能获得预期结果。

Ultimately though, there's nothing to beat experience - run your synthesiser over your code (or small parts of it) at regular intervals and see what the tool produces. 最终，没有什么可以击败的经验 - 定期运行你的合成器代码（或它的一小部分），看看工具产生了什么。