uninitialized input signal isim

Question

I am stuck with the following situation

I am designing a vhdl project for uart. There are two components namely uart_rx.vhd and uart_tx.vhd.

I suppose uart_tx goes in Mark state initially upon receiving the value '0' to signal: ready. Signal Ready is uninitialized, ie ready = 'U'.

uart_tx waits for input from uart_rx.vhd. As soon as uart_tx receives '0' from uart_rx, FSM goes to Start instead of Mark.

Here is the algorithm I've used:

if ready = o
    state <= Mark
else
    state <= Start

Answer 1

编写一个测试平台并进行初始化以准备就绪：

signal ready : std_logic := '0';