ISim shows U for all outputs

Question

I have a simple VHDL design and test bench that does not produce the expected output. ISim shows 'U' for all the outputs until the 'running' state is achieved (myState='1'). Then they show 0 and X values. The first PROCESS block should set all outputs to '0' when ENABLE is '0'. The test bench toggles ENABLE 0-1-0 to insure an event triggers the process, but the outputs stay at 'U'. Is the problem in the design, the test, or both?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TestHarness1 is
port (
    ADAT_WDCLK : in std_logic;
    ADAT_BCLK: in std_logic;
    ADAT_OUT12: in std_logic;
    ENABLE: in std_logic;

    PCM_FS : out std_logic;
    PCM_CLK : out std_logic;
    PCM_DIN : out std_logic
);
end TestHarness1;

architecture Behavioral of TestHarness1 is
    --type state is (STOPPED, RUNNING);
    signal tmp : std_logic;
    signal myState : std_logic;
begin
    PCM_DIN <= tmp; 

    -- State management process
    process (ENABLE, ADAT_WDCLK) begin -- Eval on input changes
        if (ENABLE = '0') then 
            myState <= '0'; --STOPPED;
            PCM_FS <= '0'; -- All outputs muted
            PCM_CLK <= '0';
            tmp <= '0';
        else
            if (myState = '0' and rising_edge(ADAT_WDCLK)) then
                -- Move to running state only at start of a frame
                myState <= '1'; --RUNNING;
            end if;
        end if;
    end process;

    -- Output process
    process (ADAT_WDCLK, ADAT_BCLK, myState) variable counter: integer := 0; begin
        -- Only do something if we are in running state, process above
        -- sets outputs when stopped.
        if (myState = '1') then

            -- Pass the clocks through, inverting the bit clock
            PCM_FS <= ADAT_WDCLK;
            PCM_CLK <= not ADAT_BCLK;

            -- Generate fixed bit pattern data '11000101'
            if rising_edge(ADAT_WDCLK) then
                -- This would happen naturally since there are 4 bytes per word clock
                counter := 0;
            end if;
            if falling_edge(ADAT_WDCLK) then
                -- This would happen naturally since there are 4 bytes per word clock
                counter := 0;
            end if;
            if rising_edge(ADAT_BCLK) then -- Change data state only on falling edge of output PCM_CLK
                if counter = 0 or counter = 1 or counter = 5 or counter = 7 then
                    tmp <= '1';
                else
                    tmp <= '0';
                end if;
                if (counter = 7) then
                    counter := 0;       -- Reset counter
                else
                    counter := counter + 1; -- Just inc counter
                end if;

            end if;
        end if;
    end process;
end Behavioral;

Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TH1TestBench3 IS
END TH1TestBench3;

ARCHITECTURE behavior OF TH1TestBench3 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT TestHarness1
    PORT(
         ADAT_WDCLK : IN  std_logic;
         ADAT_BCLK : IN  std_logic;
         ADAT_OUT12 : IN  std_logic;
         ENABLE : IN  std_logic;
         PCM_FS : OUT  std_logic;
         PCM_CLK : OUT  std_logic;
         PCM_DIN : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal ADAT_WDCLK : std_logic := '0';
   signal ADAT_BCLK : std_logic := '0';
   signal ADAT_OUT12 : std_logic := '0';
   signal ENABLE : std_logic := '0';

    --Outputs
   signal PCM_FS : std_logic;
   signal PCM_CLK : std_logic;
   signal PCM_DIN : std_logic;

   -- Clock period definitions. Note WDCLK is defined in terms of the bit clock
    -- to insure they are exactly in sync.
   constant ADAT_BCLK_period : time := 326 ns; -- About 3.072MHz (https://www.sensorsone.com/frequency-to-period-calculator/)
   constant ADAT_WDCLK_period : time := ADAT_BCLK_period * 64; -- 48KHz

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: TestHarness1 PORT MAP (
          ADAT_WDCLK => ADAT_WDCLK,
          ADAT_BCLK => ADAT_BCLK,
          ADAT_OUT12 => ADAT_OUT12,
          ENABLE => ENABLE,
          PCM_FS => PCM_FS,
          PCM_CLK => PCM_CLK,
          PCM_DIN => PCM_DIN
        );


   -- Clock process definitions
   ADAT_WDCLK_process :process
   begin
        ADAT_WDCLK <= '0';
        wait for ADAT_WDCLK_period/2;
        ADAT_WDCLK <= '1';
        wait for ADAT_WDCLK_period/2;
   end process;

   ADAT_BCLK_process :process
   begin
        ADAT_BCLK <= '1';
        wait for ADAT_BCLK_period/2;
        ADAT_BCLK <= '0';
        wait for ADAT_BCLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
        ENABLE <= '1';
        wait for 100 ns;
        ENABLE <= '0';
        wait for 7500 ns;
        ENABLE <= '1';


      wait for ADAT_WDCLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

ISim shows the ENABLE pulse early in the simulation, but the outputs remain 'U' until the rising edge of the WCLK with ENABLE=1. Then they start to change (as designed) but they show some X values.

Modified VHDL

For reference, here is the modified VHDL that resolves the problem of U's and X's in the simulation output. However, there is a functional problem with the PCM_DIN output... seems like it is delayed one (BCLK) cycle. I expected it to be '1' as soon as ADAT_WDCLK goes high the first time after ENABLE. But it does not go to '1' until a BLCK cycle later.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TestHarness1 is
port (
    ADAT_WDCLK : in std_logic;
    ADAT_BCLK: in std_logic;
    ADAT_OUT12: in std_logic;
    ENABLE: in std_logic;

    PCM_FS : out std_logic;
    PCM_CLK : out std_logic;
    PCM_DIN : out std_logic
);
end TestHarness1;

architecture Behavioral of TestHarness1 is
    --type state is (STOPPED, RUNNING);
    signal tmp : std_logic;
    signal myState : std_logic;
begin
    PCM_DIN <= tmp; 

    -- State management process
    process (ENABLE, ADAT_WDCLK) begin -- Eval on input changes
        if (ENABLE = '0') then 
            myState <= '0'; --STOPPED;
        else
            if (myState = '0' and rising_edge(ADAT_WDCLK)) then
                -- Move to running state only at start of a frame
                myState <= '1'; --RUNNING;
            end if;
        end if;
    end process;

    -- Output process
    process (ADAT_WDCLK, ADAT_BCLK, myState) variable counter: integer := 0; begin
        -- Only do something if we are in running state
        if (myState = '0') then
            PCM_FS <= '0'; -- All outputs muted
            PCM_CLK <= '0';
            tmp <= '0';
        elsif (myState = '1') then
            -- Pass the clocks through, inverting the bit clock
            PCM_FS <= ADAT_WDCLK;
            PCM_CLK <= not ADAT_BCLK;

            if rising_edge(ADAT_BCLK) then -- Generate fixed serial bit pattern
                if counter = 0 or counter = 1 or counter = 5 or counter = 7 then
                    tmp <= '1';
                else
                    tmp <= '0';
                end if;
                if (counter = 7) then
                    counter := 0;       -- Reset counter
                else
                    counter := counter + 1; -- Just inc counter
                end if;

            end if;
        end if;
    end process;

end Behavioral;

ISim of the above (including the internal myState signal)... why is PCM_DIN delayed one BCLK cycle?

Answer 1

Regarding the 'X' (Forcing Unknown) values you are seeing:

You are driving the signals PCM_FS , PCM_CLK and tmp from multiple processes, which results in the simulator being unable to resolve the value being driven. You need to fix this such that they are only being driven from one process, or drive 'Z' when they are not in use.

Regarding the 'U' values, they exist because you have no initial values for the signals. Once you write the signals for the first time (after the enable), they will be assigned for the first time.