I'm trying to moniter the state of this variable:
shared variable Div16 : integer := 0;
But I am recieving this error in ISim:
ISim does not yet support tracing of VHDL variables.
Can you convert the variable to a signal within the testbench file? Or is there any other way to show this value changing as a waveform?
Complete Code:
entity MAIN_UART is
generic (
DIVISOR: natural := 120 -- DIVISOR = 50,000,000 / (16 x BAUD_RATE)
-- 9600 -> 120
-- 19200 -> 60
);
port (
CLK: in std_logic; -- clock
RST: in std_logic -- reset
);
end MAIN_UART;
architecture Behavioral of MAIN_UART is
signal Top16: std_logic; -- 1 clk spike at 16x baud rate
shared variable Div16 : integer := 0;
-- constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
begin
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
Top16 <= '0'; --good
Div16 := 0;
elsif rising_edge(CLK) then
Top16 <= '0';
if Div16 = Divisor then
Div16 := 0;
Top16 <= '1'; --good
else
Div16 := Div16 + 1;
end if;
end if;
end process;
end Behavioral;
You can add:
signal Div16_signal : integer := 0;
And then at then end of your process add:
Div16_signal <= Div16;
In addition to the answer of @0xMB.
If you want iSim to offer other radices than the default, you need to declare the div16
signal as for example SIGNED and add a conversion to the variable to signal assignment.
architecture rtl of myEntity is
signal DBG_div16 : SIGNED(31 downto 0);
begin
process(clk)
variable div16 : integer := 0;
begin
-- some code
-- assign the variable to a signal, so iSim can display it's value
DBG_div16 <= signed(div16, DBG_div16'length);
end process;
end architecture;
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